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Quantitative Extraction of Bias Stress Parameters in Thin Film Transistors 10.17863/CAM.90347 Zhang, Tianwei Andrew, Flewitt Thin film transistors (TFTs) are widely used in active matrix displays and are finding applications in emerging areas of large-area electronics, such as logic. A key limitation of the practical applications of TFTs is their inherent instability under bias stress. The two leading semiconducting TFT materials for displays, hydrogenated amorphous silicon (a-Si:H) and amorphous indium gallium zinc oxide (a-IGZO), both suffer from a positive threshold voltage shift under the application of a positive gate bias, commonly called positive bias stress (PBS). The most common method for quantifying PBS is a direct current (DC) stability measurement which quantifies the threshold voltage shift by applying a gate bias for extended periods and periodically performing gate transfer measurements. Multiple parameters including threshold voltage can then be extracted as a function of stressing time. Then a thermalisation energy analysis can be used to extract the attempt-to-escape frequency and distribution of activation energies for the bias stress process. However, previous reports have used a trial and error method for estimating the attempt-to-escape frequency based on when all the threshold voltage shift curves for different temperatures overlap on a common energy axis. Obviously, the accuracy of this method is low, so a stretched exponential fitting method is applied to extract the threshold voltage shift. The accuracy of the attempt-to-escape frequency estimation is increased by an order of magnitude and hence the estimation of the activation energy distribution is also significantly improved. Despite improved accuracy in the analysis, the DC stability measurement itself is not the most accurate method for the stress test. The need to periodically remove the stressing gate bias voltage to conduct a gate transfer measurement introduces a systematic error which increases with measurement time. This can be mitigated by applying a small DC drain voltage and measuring the source current as a function of time and using this to determine the threshold voltage shift, but this assumes that the transconductance is not affected by the bias stress, which is not always the case. To eliminate this problem, a novel small-signal measurement is proposed and demonstrated in this thesis. The essential improvement is that a small signal is superposed on the constant DC stress gate voltage which results in an AC component in the source current. This AC current allows the transconductance to be continuously measured and may be combined with the DC current to determine the threshold voltage without the need for gate transfer measurements. A small-signal AC simulation result is used to illustrate the expected voltage and current waveforms for different small-signal operating points. The drain-source current decreases as the device is stressed and the threshold voltage can be extracted continuously using the peak values of voltage and current every cycle. Then, the threshold voltage shift can be plotted accordingly. Challenges with performing small-signal measurements are discussed including the high-speed current detection and noise reduction methods, and solutions are described and tested experimentally. All the difficulties have been countered and the stretched exponential fitting method is also applied in the AC measurement data processing. The result of AC matches the DC result. Moreover, with the help of the AC technique, the accuracy has been further improved the error for both attempt-to-escape frequency and activation energy with errors reduced from 6% in DC to 4% in AC. It is also the first time to plot the transconductance change as a function of time. With the help of a very high data rate in the AC measurement, the time for the stress test could also be shortened with some slight sacrifice in accuracy. There have been very few previous studies on AC TFT measurements, and those that have been published were done using a very fast on-off switching pulse gate voltage which is different from the gate AC signal applied in this thesis. It is shown that the AC measurement greatly enhances the accuracy and measurement time for TFT bias stress testing. University of Cambridge 2022-08-09 Thesis Doctoral Doctor of Philosophy (PhD) eng Chinese Scholarship Council https://www.repository.cam.ac.uk/handle/1810/342935 controlled.access https://apollo8-f-pro.lib.cam.ac.uk/bitstreams/6ce51d3e-28bd-44d4-b8fe-d36be9ccd259/download 9cde303fc4d60ba5b1111af026adedfa https://www.rioxx.net/licenses/all-rights-reserved/ Quantitative Extraction TFT characterization thin film transistors