10.1002/(ISSN)2751-9457 IFM2 Information & Functional Materials Inf. Funct. Mater 2751-9554 2751-9457 10.1002/ifm2.31 IFM231 REVIEW REVIEW Reliability challenges of gate dielectric materials in transistors Liu Ting‐Wei https://orcid.org/0009-0003-7249-8119

Ting‐Wei Liu is currently a graduate student at Institute of Semiconductors, Chinese Academy of Sciences. She received the Bachelor's Degree of Engineering in material physics from Nankai University in 2022. She is working toward the Master degree in nano science and technology with the University of Chinese Academy of Sciences. Her research interests include defect calculation and device reliability simulation.

image 1 Zhao Zhe

Zhe Zhao received his Ph.D. degree in School of Physical Science and Technology from Inner Mongolia University, Hohhot, China, in 2024. He is currently a lecturer at the School of Computer Information Management, Inner Mongolia University of Finance and Economics, Hohhot, China. His research interests include reliability of semiconductor devices and electrical transport simulation of nano devices.

image 1 Cao Ruyue

Ruyue Cao received her Ph.D. degree at Institute of Semiconductors, CAS, and is currently a Postdoctoral Researcher at University of Cambridge. Her research interests include atomistic and electronic structures of surface, interface, and defects in semiconductors, and their impact on the electrical device properties, as well as rational design of dielectrics and ferroelectrics.

image 1 2 Liu Yue‐Yang

Yue‐Yang Liu is a professor at Institute of Semiconductors, Chinese Academy of Sciences. He received his Ph.D. Degree in physics from Hunan University in 2017, and then engaged in postdoctoral research at the Institute of Semiconductors. He also worked as a visiting scholar at Lawrence Berkeley National Laboratory in the United States from 2019 to 2020, and then joined the Institute of Semiconductors formally. His research interest lies in atomic‐scale first‐principles calculation on semiconductor devices, including their interfaces, defects, and reliability.

image yueyangliu@semi.ac.cn * 1 Jiang Xiangwei xwjiang@semi.ac.cn * 3 State Key Laboratory of Semiconductor Physics and Chip Technologies Institute of Semiconductors Chinese Academy of Sciences Beijing China Department of Engineering University of Cambridge Cambridge UK Department of Mathematical and Physical Sciences National Natural Science Foundation of China Beijing China Correspondence Yue‐Yang Liu and Xiangwei Jiang. Email: yueyangliu@semi.ac.cn and xwjiang@semi.ac.cn 16 04 2025 18 02 2025 27 09 2024 06 03 2025 © 2025 The Author(s). Information & Functional Materials published by John Wiley & Sons Australia, Ltd on behalf of Zhejiang University. © 2025 The Author(s). Information & Functional Materials published by John Wiley & Sons Australia, Ltd on behalf of Zhejiang University. 2025 © 2025 The Author(s). Information & Functional Materials published by John Wiley & Sons Australia, Ltd on behalf of Zhejiang University. http://creativecommons.org/licenses/by/4.0/ This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. Abstract

The gate dielectric plays a critical role in field‐effect transistors since it determines the capability of gate control and the reliability of the device. In modern large scale integrated circuits, the stacking of high‐k oxides has become an indispensable strategy to enable the continuous shrinking of the device. However, the multiple interfaces, various kinds and large number of defects have brought about significant reliability issues such as threshold voltage shift, gate leakage current, random noise, hysteresis, fixed charges and so on. Effectively dealing with these reliability issues has become the main challenge of dielectric design. On the other hand, with the emerging of two‐dimensional (2D) channel materials, traditional oxide dielectrics turn out to be nonideal due to their surface dangling bonds. The development and design of new gate dielectrics become urgent and attractive. In this review, we will summarize the advantages and challenges of different dielectrics that are applicable to several mainstream channel materials, including Si, SiC, GaN and 2D materials. For each kind of dielectric, possible strategies to improve its reliability are discussed.

 dielectric material high‐k reliability challenges transistor National Key Research and Development Program of China 2022YFF0605800 CAS Project for Young Scientists in Basic Research YSBR‐056 MIND Project MINDKT202403