Influence of Structural Disorder on 

Charge Transport and Stability in 

Organic Field-Effect Transistors with 

Molecular Semiconductors 

 

 

 

 

Haoxin Gong 

Department of Physics 

University of Cambridge 

 

This dissertation is submitted for the degree of 

Doctor of Philosophy 

 

Darwin College                                                                                                            June 2024 



ii 

 



 

iii 

Declaration 

This thesis is the result of my own work and includes nothing which is the outcome of work 

done in collaboration except as declared in the preface and specified in the text. It is not 

substantially the same as any work that has already been submitted, or, is being concurrently 

submitted, for any degree, diploma or other qualification at the University of Cambridge or any 

other University or similar institution except as declared in the preface and specified in the text. 

It does not exceed the prescribed word limit for the relevant Degree Committee. 

 

Haoxin Gong 

June 2024



iv 

 

 



 

v 

Abstract 

Organic semiconductors (OSCs) are distinguished by the soft van der Waals interactions 

among π-conjugated moieties, garnering substantial interest for potential use in large-area and 

flexible electronics due to their inherent lightweight, versatile processing capabilities, and 

compatibility with stretchable substrates. In the realm of organic field-effect transistors 

(OFETs) using molecular semiconductors (MSCs), remarkable advancements have been made 

in enhancing charge carrier mobility through the synthesis of novel semiconducting materials, 

a refined understanding of the impact of molecular structure and packing on charge transport 

properties, as well as the optimization of device components to eliminate extrinsic factors that 

limit transport. Despite these achievements, the full potential of OSCs is often constrained by 

an incomplete comprehension of structure-property relationships and challenges posed by 

device traps and stability issues. The soft intermolecular interactions and typically large 

molecular units of molecular semiconductors create a unique charge transport regime where 

the prevalent static disorder and complex structural dynamics couple with charge carrier 

motion, fundamentally affecting the delocalization of electronic wavefunctions and the 

(opto-)electronic properties of devices on a macroscopic scale.  

 

Our systematic study, underpinned by experimental techniques and theoretical frameworks, 

delves into the charge transport mechanisms and device stability of organic thin-film transistors 

(OTFTs) fabricated from a p-type, asymmetric molecular solid, 2-decyl-7-phenyl-

benzothienobenzothiophene (Ph-BTBT-C10). The research findings indicate that the 

inhomogeneity of MSC thin films profoundly influences the temperature-dependent carrier 

mobility, transitioning from band-like transport signatures to scenarios that involve both 

delocalized and localized charge carriers as temperatures vary. These shifts across different 

transport regimes are further inferred by spectral density analyses of charge trap states near the 

band edge, derived from electrical measurements of OTFTs. Furthermore, the thesis thoroughly 

addresses the problems of charge carrier trapping and the operational stability of thin-film 



vi 

 

transistors through detailed device characterization and microscopic investigations. We 

pinpoint intrinsic origins of electronic trap states associated with net molecular dipoles and 

propose sophisticated device engineering strategies to mitigate the stress-induced degradation, 

thereby enhancing the performance and reliability of OFETs. Additionally, our research 

underscores the importance of morphology control and process optimization in overcoming the 

challenges related to the solution-based self-assembly of MSC molecules. The systematic 

exploration of thermal effects on Ph-BTBT-C10 thin films and transistors provides critical 

insights into structural transformations at elevated temperatures approaching the phase 

transition, which could be essential for developing thermally durable electronics suitable for 

applications in space exploration, smart textiles, automotive technologies, and other fields. 

Ultimately, this research aims to enhance our understanding of charge transport mechanisms 

and device degradation in organic thin-film transistors. Additionally, it seeks to pave the way 

for innovative solutions in developing next-generation organic electronics, which are essential 

for sustainable technological advancements across diverse sectors. 

 



 

vii 

Acknowledgements 

The past years at Cambridge have been a transformative journey in personal growth and 

scientific exploration. This journey would not have been possible without the support and 

collaboration of many respected individuals. I am profoundly grateful to my supervisor, Prof. 

Henning Sirringhaus, for his guidance and support throughout my PhD. Henning has given me 

the freedom to pursue my interests and ideas, from selecting my research topic to providing the 

necessary advice and encouragement when needed. The research methodology and philosophy 

he instilled will guide me in my future endeavours across various fields and career paths. 

 

I owe a special thanks to the members (and ex-members) of our lab, with whom I have 

extensively collaborated on the works presented in this thesis. I am particularly indebted to Dr. 

Xinkai Qiu, who performed delicate and superior-level Kelvin probe force microscopy 

measurements on the samples I fabricated. Our extensive discussions on the implications of the 

KPFM measurements and his numerous suggestions have helped optimize my experimental 

methodologies and guided me through periods of uncertainty caused by trivial issues in 

laboratory work. I also wish to express my gratitude to Dr. Xinglong Ren, whose erudite advice 

has almost always answered my questions regarding fundamental physics and laboratory 

practices. My thanks also go to Dr. Deepak Venkateshvaran, who not only reviewed my first-

year progress report but also provided heartfelt advice and support whenever I sought it. 

 

Reflecting on the start of my research at the MRC, I thank Gosia and Dion for training me in 

the general procedures of photolithography and electrode deposition. I am also grateful to 

Qijing for sharing his experience with drop-casting small molecule thin crystals and conducting 

electrical measurements, and to Wenjin for introducing me to the operation of our home-built 

blade coater. The everyday functioning of our lab would not have been possible without the 

diligent management of lab equipment and maintenance by Radoslav and Steve, to whom we 



viii 

 

owe a great deal of gratitude. Writing this thesis brings many cherished memories with 

wonderful colleagues to mind. I will always treasure the fruitful and enjoyable discussions with 

Mindaugas. We are the only two members in the lab focusing on solution-processed conjugated 

small molecules, and at the time of writing, we see no successors to continue our specific line 

of inquiry. The road trip to the InnoLAE 2023 conference in Cambridge was particularly 

memorable, shared with Elliot, Will, and Xinkai — it was a journey filled with laughter and 

camaraderie. The MRS Winter 2024 conference provided a heartwarming reunion with Tarig 

and Youcheng, where we enjoyed the delicious cuisine at the canteen of the Berklee College 

of Music. While I cannot mention all the incredible colleagues and friends with whom I've 

shared these golden years due to space limitations, I hold each memory close to my heart and 

am grateful for every moment spent with them. 

 

I have also been fortunate to receive great kindness and warm support from tutors and 

collaborators beyond Cambridge. I am particularly grateful to Prof. Aristide Gumyusenge for 

welcoming me into his group, the OMSE lab, at MIT for a three-month research visit. This 

experience allowed me to delve into the mixed ionic and electronic conductions in organic 

materials and their extensive applications across various fields. This opportunity would not 

have been possible without Henning's invaluable bridging and financial support. I extend my 

thanks to the OMSE lab members, especially Heejung, for her generous assistance with UV/Vis 

and XRD measurements; Mujtaba, for introducing me to the microprobe chamber; and also to 

Camille, Eric, and Rebecca for their support and camaraderie. Additionally, I am thankful to 

our collaborators at Monash University, Prof. Chris McNeill and his former group member Dr. 

Wen Liang Tan, for conducting GIWAXS measurements on my blade-coated thin films. 

 

Outside the realm of academia, I am deeply grateful to my parents for their unwavering support, 

care, and encouragement. My thoughts are constantly with my grandparents, and I wish them 

good health, high spirits, and happiness. The past few years, marked by the spread of COVID, 

have been particularly challenging for everyone involved in lab work and daily commuting. I 



 

ix 

regret that I had less time and fewer opportunities to reunite and celebrate the important 

moments with my dear family and close friends. 

 

Finally, I am profoundly thankful to Jian, who has brought colour to my life, brightening even 

the greyest days. I eagerly anticipate starting a new chapter of life with her by my side.



x 

 

 



 

xi 

Table of Contents 

 

Table of Contents ...................................................................................................................... xi 

Chapter 1 Introduction ........................................................................................................... 1 

Chapter 2 Background and Theory ........................................................................................ 5 

2.1 Charge transport in high-mobility molecular semiconductors ..................................... 5 

2.1.1 Dichotomy between hopping and bandlike transport ........................................... 6 

2.1.2 Dynamic disorder and the transient localization scenario .................................. 12 

2.1.3 Disordered Models .............................................................................................. 18 

2.2 Device physics of organic field-effect transistors ...................................................... 21 

2.2.1 Operating principles of a unipolar OFET ........................................................... 21 

2.2.2 Charge injection and contact resistance .............................................................. 25 

2.2.3 Nonideal behaviours in OFETs ........................................................................... 30 

Chapter 3 Experimental Methods ........................................................................................ 35 

3.1 Solution-processed thin film deposition .................................................................... 35 

3.2 Device fabrication ...................................................................................................... 40 

3.3 Electrical characterization .......................................................................................... 43 

3.4 Scanning probe microscopy ....................................................................................... 46 

3.5 X-ray diffraction and spectroscopic techniques ......................................................... 50 

Chapter 4 Characterizing Charge Transport and Trap Dynamics in OFETs across 
Temperature Variations ........................................................................................................... 53 

4.1 Introduction ................................................................................................................ 53 

4.2 Investigating the temperature dependence of field-effect mobility ........................... 58 

4.3 Analysing trap density of states using the Grünewald approach ............................... 68 

4.4 Summary .................................................................................................................... 75 

Chapter 5      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film 
Transistors ...............................................................................................................................  79 

5.1 Introduction ................................................................................................................ 79 

5.2 Examining operational stability through device engineering .................................... 83 

5.3 Revealing structure-dependent charge trapping through KPFM ............................... 94 

5.4 Summary .................................................................................................................. 108 



xii 

 

Chapter 6 Thermal Effects and Phase Transitions in Organic Thin-Film Transistors: 
Exploring Transport Properties and Structural Dynamics ..................................................... 111 

6.1 Introduction .............................................................................................................. 111 

6.2 Evaluating FET performance at elevated temperatures ........................................... 115 

6.3 Analysing structural transformations upon thermal treatment ................................. 121 

6.4 Summary .................................................................................................................. 132 

Chapter 7 Conclusions and Outlook .................................................................................. 135 

References 140 

Appendix A      Supplementary Information for Experimental Chapters ................................ A1 

A.1 Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature 
Variations ............................................................................................................................ A1 

A.2 Charge trapping and bias stress degradation in Ph-BTBT-C10 thin-film transistors A4 

A.3 Thermal Effects and Phase Transitions in Organic Thin-Film Transistors: Exploring 
Transport Properties and Structural Dynamics ................................................................... A9 

Appendix B      Further Experimental Investigations .............................................................. B1 

B.1 Transfer of Ph-BTBT-C10 thin films via a wet-etching method ............................... B1 

B.2 Thermoelectric voltage characterization of ion-gel gated Ph-BTBT-C10 ................. B6 



 

Chapter 1 Introduction 

Since the initial discoveries concerning the electrical conductivities of organic materials, either  

through the use of charge injection electrodes or doping with halogens1–3, organic 

semiconductors (OSCs) – once presumed to be electrically insulating – have been widely 

applied in a myriad of (opto-)electronic devices, including organic light emitting diodes 

(OLEDs)4,5, organic photovoltaics (OPVs)6,7, and organic field-effect transistors (OFETs)8,9. 

Compared to the inorganic counterparts, OSCs hold significant advantages regarding the 

versatility of synthesis processes10,11, reduced production costs through solution-processing 

techniques12,13, and compatibility with transparent and plastic substrates14,15. These attributes 

render them especially promising for flexible electronic applications. Consequently, major 

high-tech companies such as Samsung and Universal Display Corporation have made 

substantial investments in developing low-cost, high-performance organic electronic devices. 

This booming market, already worth several billion dollars, is expected to expand rapidly. 

Organic electronics are increasingly becoming part of our daily lives, evident in applications 

ranging from smartphone displays, coloured lighting solutions, portable solar cells, to wearable 

health monitoring devices. 

 

Organic semiconductors encompass a broad family of conjugated molecules and polymers, 

primarily held together by van der Waals forces. In these materials, the σ electrons form a 

relatively planar skeleton, while the delocalized π electrons extend in a halo of electronic 

density above and below this molecular plane. The frontier molecular orbitals, specifically the 

lowest unoccupied molecular orbital (LUMO) or highest occupied molecular orbital (HOMO) 

of adjacent molecules can interact weakly and form narrow conduction (valence) band, whose 

width is directly coupled to the strength of π–π interactions. These interactions are pivotal in 

defining the optical properties, redox potentials, chemical reactivity, and electronic transport 



2  Introduction 

 

characteristics of OSCs. Recent studies have delved deeply into the transport physics of high-

mobility small molecules and conjugated polymers, revealing the intricate factors that 

influence charge carrier mobilities in these materials16–19. Charge transport properties of 

molecular semiconductors (MSCs) are directly linked to the molecular geometry and the 

crystalline assembly of molecules20. Although the molecular structure is crucial, it is the 

packing of individual moieties within the solid state that determines the overlap of 

neighbouring orbitals and subsequently defines the pathways for charge transport. Furthermore, 

these molecular units are often large, comprising hundreds of atoms, and exhibit complex 

structural dynamics with various intensive vibrational modes that are thermally accessible at 

room temperature21,22. This complexity leads to a strong coupling between electronic and 

structural dynamics, giving rise to unique and fascinating phenomena within these molecular 

solids.  

 

While OLEDs and OPVs are among the first organic electronics products achieving or 

approaching market success, organic field-effect transistors remain a cornerstone component, 

essential for creating logic circuits and smart pixels in displays. Achieving high field-effect 

mobility is imperative, as it impacts not only the clock frequency of circuits but also the current 

delivery to display pixels. Today, optimizations in the design of OSCs and the OSC–dielectric 

interface have led to remarkable advancements. High electron and hole mobilities have been 

achieved in both organic single crystals (10–50 cm2 V-1 s-1)23,24 and solution-processed 

semiconducting polymers (up to 5 cm2 V-1 s-1)25,26 in research settings, rivalling the 

performance of amorphous silicon thin-film transistors. However, technological transfer of 

these organic transistors still faces a series of challenges. One major issue is the variability in 

conductivity due to randomly deposited layers of molecules or polymers, leading to poor 

reproducibility across processes and between devices. Moreover, in practical applications, 

static disorder such as chemical impurities and structural defects introduces electronic states 

within the band gap of organic semiconductors. These states can localize charge carriers and 

hinder their transport27–29, preventing OSCs from realizing their intrinsic mobility limits. 

Charge carrier trapping is a ubiquitous phenomenon that affects the performance and stability 

of OFETs. While our understanding of charge carrier traps is gradually improving, a deeper 



Introduction   3 

 

  

comprehension of the specific mechanisms and dynamics of trap formation, as well as the 

energy landscapes involved remains decisive in evaluating the fundamental performance limits 

of OSCs and engineering high-performance devices suitable for commercialization. 

 

In this thesis, we delve deeply into the charge transport physics, device stability issues, and 

structure-property relationships in organic thin-film transistors fabricated using a high-mobility 

molecular semiconductor, 2-decyl-7-phenyl-benzothienobenzothiophene (Ph-BTBT-C10). 

This organic small molecule was designed and synthesized by Iino and his collaborators in the 

early 2010s and has become a commercial product for field-effect transistor applications30.  Its 

unique molecular shape, characterised by asymmetric substitution with a phenyl group and a 

decyl chain at either end of the conjugated core, leads to a bilayer herringbone packing within 

the crystalline phase. Additionally, the conformational freedom of the decyl chain enables a 

highly-ordered smectic liquid crystalline phase at elevated temperatures, offering more 

avenues for structural investigations and device measurements. The structure of this PhD thesis 

is as follows: 

Chapter 2 reviews the charge transport theories pertinent to molecular semiconductors, 

highlighting the widely recognized transient localization scenario. It also thoroughly explores 

the device physics of OFETs.  

Chapter 3 describes the experimental techniques used for thin film and device fabrication, 

electrical testing, and microscopic and spectroscopic characterization of Ph-BTBT-C10 thin 

films.  

Chapter 4 investigates the charge transport mechanisms in Ph-BTBT-C10 thin films, focusing 

on variations in crystallinity and employing variable temperature measurements down to 80 K. 

It also includes an analytical analysis of the spectral density of charge trap states derived from 

electrical measurements.  

Chapter 5 applies device engineering techniques and surface electrostatic potential mapping 

via Kelvin probe force microscopy to systematically examine the notorious bias stress effect in 



4  Introduction 

 

OFETs, linking differences in trapping dynamics to variations in molecular orientation and 

dipolar disorder.  

Chapter 6 extends the temperature-dependent measurements of thin-film transistors to 

elevated temperatures approaching the crystalline to smectic liquid crystalline phase transition. 

It correlates the observed trends in device performance with subtle morphological 

transformations in the thin film samples as the temperature increases.  

Chapter 7 discusses the implications of our research findings and outlines future directions of 

study, particularly focusing on enhancing the functionalities and advancing the 

commercialization of molecular semiconductors and organic semiconductors more broadly. 



 

Chapter 2 Background and Theory 

2.1 Charge transport in high-mobility molecular 

semiconductors 

Molecular semiconductors (MSCs) are notable for their unique solid-state physical and 

optoelectronic properties, largely governed by van der Waals interactions among pi-conjugated 

molecular moieties. Understanding molecular structure-property relationships and the 

underpinning charge transport physics is particularly vital for advancing their applications in 

fields like displays, sensors, and electronic skin. Over recent decades, research focused on 

exploring molecular structures, optimizing device configurations, and minimizing impurities 

and structural defects has significantly enhanced charge carrier mobility, from the small values 

observed in early organic field-effect transistors (OFETs) (10-6~10-5 cm2 V-1 s-1) to levels 

exceeding amorphous silicon (over 1~10 cm2 V-1 s-1). Such magnitudes are inconsistent with 

the Boltzmann transport theory involving fully delocalized Bloch electrons or incoherent 

charge hopping among localized sites, historically sparking intense debates about the extended 

versus localized nature of charge carriers. A tight-binding Hamiltonian that serves as an 

illustrative framework for describing the electronic properties of molecular solids is given 

by17,31,32 

, ,
, ,

1ˆ ˆˆ ˆ ˆ ˆ ( )
2

1 1ˆ ˆ ˆ ˆˆ ˆ ˆ ˆ( ) ( ) ,
2 2

i i i ij i j M M M
i ij M

i M M M i i ij M M M i j
i M i j M

H a a J a a b b

g b b a a g b b a a

   

   



   

   

  

 


                      (2.1) 

where εi represents the on-site electronic energy of the charge carrier; Jij denotes the transfer 

integral characterizing the intermolecular electronic interactions between neighbouring 

molecules at sites i and j; ℏ is the reduced Planck constant; ωM is the phonon frequency of mode 



6  Background and Theory 

 

M; ˆia ( ˆia ) is the creation (annihilation) operator for a charge carrier at site i; ˆ
Mb ( ˆ

Mb ) is the 

phonon creation (annihilation) operator; ,i Mg ( ,ij Mg ) correspond to the local (nonlocal) 

electron-phonon coupling constants, which characterize the interaction strengths between 

charge carriers and intramolecular (intermolecular) vibrations. Here. the first two terms of the 

Hamiltonian denote the electronic components, the third term represents lattice phonons, and 

the final two terms refer to the local and nonlocal electron-phonon couplings, respectively. The 

closely matched magnitudes of these Hamiltonian components make most traditional 

approximations based on energy scale separation ineffective32, thus rendering the theoretical 

elucidation of charge transport a challenging task. In Chapter 2.1, we aim to provide a concise 

overview of various theoretical approaches and physical insights pertinent to charge transport 

in high-mobility MSCs. A particular emphasis is placed on the impact of dynamic disorder 

resulting from the coupling of carrier motion with intermolecular vibrations, as we explore the 

evolving concept of transient (de)localization. We also discuss experimental techniques 

developed to probe the delocalized or molecular character of charge carriers. The section 

concludes by touching briefly on the role of static disorder and the associated localized 

electronic states in charge transport in actual MSC samples. By examining the theoretical 

foundations, we underscore the continuous need to mitigate detrimental factors and explore 

potential enhancements in carrier transport, aiming to unlock the full potential of molecular 

semiconductors and propel technological innovations. 

 

2.1.1 Dichotomy between hopping and bandlike transport 

In highly ordered inorganic semiconductors, where atoms are arranged with high periodicity 

within a crystalline lattice and atomic orbitals overlap significantly to form quasi-continuous 

energy bands, charge carriers can propagate through these bands as Bloch waves, characterized 

with well-defined momentum k and energy band dispersion E(k). Their dynamics can be 

quantitatively described by the semiclassical Boltzmann equation33, where a charge carrier is 

treated as a particle with an effective mass m* transporting and experiencing collisions or 

scattering with impurities or lattice phonons (Fig. 2.1a, upper panel). These interactions reduce 



Background and Theory   7 

 

  

the charge carrier mobility µ, which is expressed by the Drude formula: µ = eτ/ m*, where τ 

represents the time interval between two successive scattering events. As the temperature T 

increases, scattering becomes more profound, leading to a simultaneous decrease in mobility 

(Fig. 2.1c, left): 

,0 3nT n                                                                      (2.2) 

where different n values are associated with various scattering mechanisms. Such band-like, 

negative µ – T dependence has also been observed in field-effect transistor measurements of 

some organic single crystals or thin films across a wide temperature range34–37. Nevertheless, 

in molecular semiconductors, molecules are held together by weak van der Waals interactions, 

leading to weaker intermolecular electronic couplings and narrower bandwidth (ranging from 

10 to 200 meV 38) compared to their inorganic counterparts. The strength of the transfer 

integrals, which measures the propensity for charge transfer, is determined by the wavefunction 

overlap of orbitals from neighbouring molecules, which is critically influenced by molecular 

geometry and packing motifs17,19–21. Given the softness of intermolecular interactions and 

substantial lattice motions at room temperature, fully delocalized band transport becomes 

untenable even for ultrapure molecular crystals. The inherent large scatterings can result in a 

carrier mean-free-path that does not exceed the intermolecular spacing, falling below the Mott-

Ioffe-Regel (MIR) limit39. Based on a one-dimensional model of rubrene40, the room-

temperature carrier mobility in accordance with the MIR limit was calculated to be 

approximately 23 cm2 V-1 s-1, representing a lower threshold for the applicability of band theory. 

 

In view of the sensitivity of charge motion to lattice dynamics in molecular crystals, the 

quasiparticle formed by a charge carrier bounded to a short-range deformation of the crystalline 

lattice has historically been termed a (Holstein) polaron41,42. In the low temperature limit (T → 

0), polaronic states retain some degree of delocalization, allowing the propagation of polarons 

to be understood by band transport features, with mobility decreasing in a power-law manner 

with increasing temperature. As the temperature rises further, enhanced polaron localization 

effects manifest as significant band narrowing, insufficient to sustain delocalized states. 



8  Background and Theory 

 

Consequently, charge transport transitions to a sequence of uncorrelated hops (Fig. 2.1a, lower 

panel), and the mobility exhibits an Arrhenius-like (thermally activated) temperature 

dependence ( ln 1 / T   ). In the context of the semiclassical electron-transfer theory 

proposed by Marcus43, the hopping rate is given by  

1/22

exp
4hop

B B

J
k

k T k T

 


   
    

   
，                                         (2.3) 

where kB is the Boltzmann constant; λ denotes the reorganization energy which serves as a 

global measure of the local electron-phonon coupling and is much greater than the magnitude 

of the transfer integral in this scenario. The reorganization energy accounts for the geometric 

relaxation of the molecules involved in charge transfer and the change in nuclear polarization 

of the surrounding medium17,21. An equivalent concept for describing the stabilization energy 

due to charge localization on a single lattice site is known as the polaron binding energy, Epol, 

2

,

1

2pol M i M
M

E g
N

  .                                             (2.4) 

At sufficiently high temperatures such that the thermal energy becomes large enough to 

dissociate the polaron, carrier transport is dominated by a residual scattering regime with 

3/2T  (Fig. 2.1c. right).  

 

 

 



Background and Theory   9 

 

  

 

Figure 2.1. a, Schematics illustrating two transport mechanisms: band transport (upper), where delocalized charge 

carriers occasionally encounter back-scattering from phonons or defects; and hopping transport (lower), where 

localized carriers are thermally activated to move via vibrationally assisted hopping. b, Chemical structures of 

some well-studied p-type molecular semiconductors. c, Temperature dependence of charge mobility as predicted 

by band-like (left) and small polaron (right) models. T1 and T2 are the associated transition temperatures within 

the Holstein polaron mechanism. Adapted and reproduced from ref. 17. 

 

Although a few reports, based on angle-resolved ultraviolet photoelectron spectroscopy, 

suggested that the energy dispersion of the highest occupied molecular orbital (HOMO)-

derived band decreases with rising temperature44,45 – ostensibly supporting polaronic band 

narrowing – the bandwidth reduction may indeed arise from thermal expansion of the 

crystal46,47. Additionally, the effects of nonlocal electron-phonon coupling resulting from 

molecular vibrations were overlooked in the original small polaron formalism48,49. Attempts to 

extend the microscopic transport theory to include their contributions have been made by 

researchers such as Munn and Silbey50, and Hannewald and Bobbert51. However, specific 

prerequisites for these polaron transformation approaches, such as vibrational relaxation 

occurring faster than the hopping rate, apply to high-frequency intramolecular vibrations but 



10  Background and Theory 

 

are inapplicable to slow intermolecular motions32,40. Thermal fluctuations of the transfer 

integrals take place on the same timescale as the carrier movements and are notably large in 

amplitude (on the order of 0.1-0.2 Å at room temperature), as indicated by theoretical 

calculations21 and thermal diffuse scattering in electron diffraction patterns22,52. An ideal theory 

for describing the electron-phonon coupling in molecular semiconductors should encompass 

both intra- and inter-molecular vibrations across a broad range of energies.  

 

We conclude this section by highlighting a few experimental techniques that showcase either 

delocalized band-like or strongly localized transport features in molecular semiconductors. 

Each technique provides distinct energetic and temporal insights into the behaviour of charge 

carriers. In addition to the well-documented negative temperature dependence of field-effect 

mobility, an ideal Hall effect provides solid evidence of band-like transport. This is observed 

when the carrier density or mobility extracted from Hall measurements matches the 

corresponding FET values, as demonstrated in Fig. 2.2a (right) with a single-crystal rubrene 

device. The Hall effect emerges from delocalized band carriers that experience the Lorentz 

force, generating a transverse Hall voltage. It is also important to note that localized charge 

carriers may drift upon the transverse electric field and partially screen the Hall voltage, leading 

to a sizeable discrepancy with FET measurements53. Hence, improved measurement setups, 

such as those involving an AC magnetic field, a DC source-drain current excitation, and phase-

sensitive detection of the Hall voltage (as illustrated in Fig. 2.2a left), along with enhanced data 

analysis approaches, are necessary for reliably extracting the Hall mobility and interpret its 

temperature dependence54,55. Besides, field-induced electron spin resonance (ESR) 

measurements probe the interactions of unpaired electron spins with an external magnetic field. 

Figure 2.2b displays an example device structure using a pentacene thin-film transistor, 

illustrating the magnetic field geometries along with gate voltage- and temperature-dependent 

ESR spectra, as revealed by Matsui et al. in a prior study. Careful analysis of the spectra 

linewidth with Lorentzian or Gaussian models can reveal details about the spatial extent of the 

electronic spin wavefunction56–58 (ranging from a few to 20 molecules) and the typical 

residence time of charge carriers at trapped sites59,60. Charge modulation spectroscopy 

characterizes the degree of molecular reorganization and polarization associated with polaron 



Background and Theory   11 

 

  

formation. As exemplified in Fig. 2.2c, this technique probes distinctive sub-bandgap optical 

absorption from localized polaronic levels (ΔT/T < 0) and bleaching of the neutral molecule π-

π* transition (ΔT/T > 0), based on the modulation of gate voltage/carrier concentration61–64. 

Meneau et al. analysed the spectral shapes of several pentacene derivative thin films at low 

temperatures65. They inferred that in some molecular systems charge carriers are localized onto 

individual molecules, giving rise to absorption features similar to those of radical 

cations/anions in solution, whereas in certain materials the wavefunction of charge carriers 

retains some degree of delocalization even at low temperatures, exhibiting characteristics akin 

to those observed under room temperature. Another optical indicator of charge localization is 

the suppression of the real part of the optical conductivity in the far-infrared range at room 

temperature, as shown by the spectra in Fig. 2.2d at 294 K. In contrast, this attenuation nearly 

disappears at low temperatures (refer to the 50 K spectra) due to reduced thermal molecular 

motions, as rationalized by the Drude-Anderson model66,67. Such non-Drude optical response 

provides direct experimental evidence of dynamic disorder-limited charge transport in 

molecular crystals, which is the essence of the transient localization model discussed later. 

Furthermore, techniques immune to contact issues, such as Terahertz electromodulation 

spectroscopy68 and time-resolved microwave conductivity measurement69, have been 

introduced to extract the intrinsic transport parameters in molecular semiconductors. 

 



12  Background and Theory 

 

 

Figure 2.2. Overview of some techniques developed for studying charge transport properties in molecular 

semiconductors. a, ac-Hall effect measurement of a single-crystal rubrene field-effect transistor (FET). b, Field-

induced electron spin resonance spectroscopy of a pentacene thin-film transistor (TFT). c, Charge modulation 

spectroscopy of a TIPS-pentacene FET. d, Optical-pump terahertz-probe spectroscopy of a rubrene single crystal. 

Adapted from ref. 54,59,63,67. 

 

2.1.2 Dynamic disorder and the transient localization scenario 

In molecular semiconductors, fluctuations in the transfer integral due to thermal motion of 

molecules can be as large as the transfer integral itself (Fig. 2.3a), and this (off-diagonal) 

dynamic disorder emerges as one of the primary limiting factors for charge mobility. Under 

linear approximation, the modification of the transfer integral between two electronic states i 

and j due to nonlocal electron-phonon couplings can be expressed as: 

0
.ij ij ij M M

M

J J g Q  ,                                                     (2.5) 

where QM denotes the associated normal mode coordinate. Hence, a global measurement of the 

fluctuations in Jij provides a quantitative assessment of the non-local dynamic disorder: 



Background and Theory   13 

 

  

 
2

2 .2 coth
2 2

ij M M
ij ij ij

M B

g
J J

k T


 

    
 

 
 .                             (2.6) 

 

The transient localization (TL) scenario has been developed to account for this strong non-

local electron-phonon coupling in the transport regime where the transfer integral is moderate 

and close in magnitude to the reorganization energy. In 2006, Troisi and Orlandi pioneeringly 

proposed that thermal molecular motions can disrupt the translational symmetry of the 

electronic Hamiltonian, thereby dynamically localizing charge carriers70. They constructed a 

semiclassical model that mimics a one-dimensional stack of planar conjugated molecules to 

compute the charge carrier mobility in the presence of intermolecular vibrations (Fig. 2.3b), 

and the model adeptly explains both the band-like temperature dependence of mobility and 

localized spectroscopic features. To address the limitations of this model, such as its classical 

treatment of vibrations which restricts the validity to high temperatures, and its approximation 

of one-dimensional systems, Troisi later demonstrated that charge diffusion by dynamic 

disorder is a feature inherent in the basic Holstein formalism71, and extended the semiclassical 

theory to higher dimensions to accurately reproduce the experimentally determined mobility in 

rubrene72. Meanwhile, Fratini and Ciuchi also highlighted that this intermediate charge 

transport regime in high-mobility MSCs can be understood through the co-existence of 

extended and incoherent states, which are dynamically affected by thermal lattice disorder73. 

In 2011, these two researchers, along with Mayou, presented the rudiments of the transient 

localization framework74. In their work, the time-dependent quantum diffusion of electrons is 

linked to the real part of the optical conductivity by virtue of the Kubo formula. Mixed 

quantum-classical simulations based on the Ehrenfest approach indicated that in the presence 

of dynamic disorder, charge carriers are temporarily localized up to the timescale of molecular 

vibrations, after which charge diffusion resumes (Fig. 2.3d). To bridge the transient localization 

and diffusive regimes, a relaxation time approximation (RTA) has been introduced. This 

approximation models the system dynamics as a decay over time from a reference state that 

depicts a localized system with static disorder only, akin to the description of Anderson 



14  Background and Theory 

 

localization. Electrons susceptible to localization can exploit lattice vibrations to diffuse freely 

over a distance of L(τin), with a trial rate of 1/τin, where τin denotes the inelastic scattering time 

associated with dynamical lattice motions (Fig. 2.3c). The resulting mobility is expressed as 

 2

2
in

RTA
B in

Le

k T





 .                                                      (2.7) 

where e represents the elementary charge. Incorporating extrinsic disorder into the transient 

localization scenario leads to a crossover from the intrinsic power-law dependence of mobility 

on temperature, persisting at high temperatures, towards a thermally activated behaviour 

caused by carrier trapping at low temperatures75. The framework nicely agrees with the finite 

frequency peak observed in rubrene in optical conductivity experiments76. 

 

 

 

 

 

 



Background and Theory   15 

 

  

 

Figure 2.3. Theoretical development of the transient localization model. a, Calculated transfer integrals for hole 

and electron transfer in a tetracene cofacial dimer, plotted as a function of the relative long-axis displacement. b, 

Schematic of the one-dimensional charge transport model proposed by Troisi and Orlandi, where the transfer 

integral j between neighbouring molecules at a separation a is linearly modulated by their relative displacement 

ui-ui+1 with the electron-phonon coupling constant α. c, Schematic of the transient localization transport 

mechanism. d, Left: Time-dependent quantum spread of the electronic wavefunction calculated via the Ehrenfest 

approach (black dotted curve), the relaxation time approximation (grey curve), and for static molecular 

displacements (white dashed curve). Middle: Corresponding instantaneous diffusivity across three distinctive 

regimes. Right: Optical conductivity obtained from the Drude-like response (dashed curve), in the limit of static 

localization (dotted curve), and via the Kubo formula in the TL scenario (solid curve). Adapted from ref. 17,40. 

 

Equation 2.7 suggests that intuitive strategies for enhancing mobility include optimising the 

transfer integrals and reducing the coupling with molecular vibrations to extend the transient 

localization length, L(τin), and tightening intermolecular bonds to increase the vibrational 

frequency, which is inversely proportional to τin
40. A map of L2(τin) for some high-mobility 

molecular semiconductors in a generic two-dimensional system has been illustrated to identify 

preferential patterns of transfer integrals that offer the greatest resilience to quantum 

localization effects77 (Fig. 2.4a). Unlike the conventional strategies of simply increasing the 

magnitude of transfer integrals, an optimal configuration for mitigating the impact of off-



16  Background and Theory 

 

diagonal dynamic disorder involves achieving an isotropic distribution of nearest-neighbour 

transfer integrals (similar in magnitude and identical in sign).  

 

Accurately evaluating dynamic disorder requires experimental information on the normal 

modes and detailed knowledge of the gradient of the transfer integrals. Sophisticated 

techniques such as Raman spectroscopy78,79, terahertz time-domain spectroscopy80, inelastic 

neutron81 or X-ray82 scattering have been effectively utilized to probe low-energy phonons in 

molecular crystals. Schweicher and D’Avino et al. conducted vibrational spectroscopy 

measurements and quantum mechanical simulations to analyse the low-frequency 

intermolecular vibrational modes and the corresponding mode-resolved electron-phonon 

coupling strength83 (Fig. 2.4b). They identified a long-axis sliding motion between 

neighbouring molecules as the “killer” phonon mode, with wavenumbers of 23 and 24 cm-1 

denoted in Fig. 2.4b for two dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) 

derivatives. The killer phonon mode constitutes noticeably to the total dynamic disorder in 

certain alkylated molecules. This study introduced another criterion for enhancing charge 

mobility within the transient localization scenario: minimising the energetic disorder, 

characterized by the relative fluctuations in the magnitude of the transfer integral, σ/J. Inspired 

by the critical role of 'killer' modes, researchers have intensified efforts in this domain. These 

initiatives involve optimizing molecular designs to suppress detrimental motions84,85, 

pinpointing key vibrational modes causing significant fluctuations in electronic coupling across 

different materials86,87, devising new methods to evaluate the impact of single atomic 

wavefunctions on electron-phonon couplings88, and refining the workflow for simulating and 

visualizing dynamic disorder89. 

 

Heated discussions and experimental verifications of the transient localization scenario 

continue to unfold. The TL scenario has recently been integrated with the Bloch-Boltzmann 

theory in the limit of low electron-phonon scattering90, forming a continuous transport phase 

diagram for MSCs (Fig. 2.4c). Bittle et al. explored the correlation between intermolecular 

phonons and anisotropic mobility in tetracene, discovering that electronic interactions and 



Background and Theory   17 

 

  

ensuing charge transport are directionally influenced by specific phonons91.  Ren et al. observed 

a reduction in hole mobility of rubrene after 13C isotopic substitution, which was attributed to 

a redshift in vibrational frequencies, aligning with the predictions of TL theory92. To 

numerically simulate charge dynamics over the transition between the TL scenario and the 

small polaron hopping regime, Giannini et al. developed a fragment orbital-based surface 

hopping approach and described the behaviour of charge carriers as flickering polarons 

constantly varying in shape and extensions due to thermal disorder93. Coupled with time-

resolved photoconductivity measurements, Giannini and Di Virgilio et al. confirmed the 

significance of sign combinations and isotropy of nearest-neighbour transfer integrals in 

determining the temperature dependence of intrinsic mobility94. They concluded that a high 

density of thermally accessible delocalised states is beneficial for achieving high mobilities in 

chemically similar materials, as evidenced by the comparison of DNTT and C8-DNTT-C8 in 

Fig. 2.4d. The concept of dynamic disorder, which portrays transiently localized charge carriers 

in a slowly evolving electrostatic landscape, has also inspired extensions in other material 

systems like semiconducting conjugated polymers95,96 and halide perovskites97. This notion has 

recently been applied to exciton transport processes, where exciton–phonon couplings enable 

localized excitons to temporarily access higher-energy delocalized states and traverse large 

distances98. Despite these advancements in the TL scenario, many nuances of charge transport 

in MSCs remain elusive. In response, some researchers have proposed alternative theories that 

aim to establish a unified framework for diverse transport regimes, including quantum nuclear 

tunnelling mechanisms99, partially dressed polaron models47, or the density matrix 

renormalization theory100, each offering different perspectives on the complexities of charge 

dynamics. 

 

 



18  Background and Theory 

 

Figure 2.4. Exploring the origin of varying transport properties within the TL scenario. a, Transient localization 

length squared L2
τ along the Jb=Jc cut of a 3D spherical mapping, shown as a function of the angle θ = arccos(Ja/J) 

with varying J. Experimental values of representative MSCs are marked with respective symbols. b, Electron–

phonon coupling maps and identification of most detrimental modes in DNTT and C8-DNTT-C8. c, Regimes of 

room temperature charge transport in two-dimensional organic semiconductors, featuring a crossover region (blue 

shaded area) that denotes dynamic localization corrections to the band theory. d, Violin plots of the inverse 

participation ratio (IPR) distribution as a function of temperature for DNTT and C8-DNTT-C8. A larger IPR 

indicates more delocalized states that are thermally accessible. Adapted from ref. 77,83,90,94. 

 

2.1.3 Disordered Models 

So far, our discussion has only considered scenarios where chemical and structural defects are 

absent, and spatial variations of electronic energy from site to site are minimal. However, 

organic semiconductor samples typically exhibit unavoidable static disorder, which induces a 

considerable proportion of localized electronic states, making the hopping motion of charge 

carriers essential in determining the overall transport properties. According to the multiple-

trap-and-release (MTR) model, charge transport is governed by the simultaneous trapping and 

releasing of charge carriers, where only those thermally activated into the band contribute to 

transport101 (Fig. 2.5b). This model is also known as the mobility edge model102, where the 



Background and Theory   19 

 

  

‘mobility edge’ refers to the energy level that separates upper delocalized (band) electronic 

states from lower localized (trap) states. Here, the effective mobility is determined by the 

fraction of carriers within the extended band states103,104: 

0
band

MTR
trap band

n

n n
 


 ,                                                 (2.8) 

where µ0 denotes the intrinsic (trap-free) mobility, nband and ntrap indicate the density of charge 

carriers within the band states or retained by shallow trap states, respectively. In materials with 

significant disorder, charge transport is typically described as thermally activated hopping 

among the manifold of localized states (e.g. Fig. 2.5c and d). This description is further refined 

using approaches such as kinetic Monte Carlo simulations105, the concept of a transport level106, 

effective-medium theory107, or percolation theory108. These methods help to account for the 

energetic spectrum of localized states alongside a Marcus-like or Miller-Abrahams109 charge 

transfer rate. The latter formalism applies particularly to scenarios with relatively weak 

electron-phonon coupling and low temperatures. The Miller-Abrahams hopping rate νij from 

site i to site j is given by 

0

2
exp

2
j i i jij

ij
B

r

k T

   
 



   
   
 
 

 ,                                       (2.9) 

where ν0 represents the attempt-to-escape frequency; rij is the separation between two sites; α 

is the localization radius of a charge carrier; εi and εj are the corresponding energies of these 

sites, and the influence of an electric field can also be included.  

 



20  Background and Theory 

 

Figure 2.5. Schematics of band-like transport (a), the multiple-trap-and-release model (b), and two examples of 

disordered transport models – variable range hopping (c) and Bässler's Gaussian disorder model (d). Adapted 

from ref.110. 

 

This section does not aim to provide a comprehensive review of disordered transport models, 

as they are more relevant to charge transfer processes in semicrystalline or amorphous organic 

materials. The key point here is that static disorder, often resulting from chemical impurities 

or structural inhomogeneities, may predominately impact charge transport in molecular 

semiconductors. Meticulous considerations are necessary when interpreting experimental 

studies, especially at the thin-film device level. It is crucial to devise more sophisticated 

experiments that perturb the materials in highly controlled ways, minimizing the inadvertent 

introduction of static disorder, to better understand intrinsic charge transport physics across 

various transport regimes. 

 



Background and Theory   21 

 

  

2.2 Device physics of organic field-effect transistors 

Organic field-effect transistors (OFETs) have been a focus of consistent attention and 

remarkable development since their inception in the 1980s. On one hand, OFETs hold 

tremendous technological appeal as they form the foundational elements of electrical on/off 

switches in a wide range of applications. The most promising ones including active-matrix 

organic light-emitting diode displays, radio-frequency identification tags, as well as novel 

sensing and memory devices111–113. On the other hand, OFETs serve as excellent platforms for 

exploring intriguing transport physics in organic semiconductors, offering precise control over 

the charge density through voltage modulation. In Chapter 2.2, we delve into the basic 

operating principles of OFETs and outline the key figures of merit during DC operation. We 

then explore the charge injection mechanisms from metallic electrodes, addressing the 

notorious issue of contact resistance through discussion on its causes, characterization methods 

and mitigation strategies. Furthermore, we examine some nonideal features observed in the 

current-voltage characteristics. The chapter concludes by emphasizing the comprehensive 

considerations necessary for reporting high-performance OFETs, ensuring an accurate 

understanding of their behaviour and performance metrics.  

 

2.2.1 Operating principles of a unipolar OFET  

An organic field-effect transistor is a three-terminal device comprising an organic single crystal 

or thin film as the active layer, with three contacts known as source, drain, and gate, and a gate 

dielectric sandwiched between the semiconductor and the gate terminal. Depending on the 

arrangement of these three contacts relative to the semiconductor layer, FET geometries are 

classified as either coplanar or staggered. This classification further divides into distinct 

architectures (Fig. 2.6a):  bottom gate, bottom contact (BGBC); top gate, top contact (TGTC); 

and bottom gate, top contact (BGTC); top gate, bottom-contact (TGBC). Unlike the classical 

metal-oxide-semiconductor field-effect transistor (MOSFET) that operates via an inversion 

layer at the semiconductor-insulator junction114, OFETs primarily use intrinsic organic 



22  Background and Theory 

 

semiconductors and function in the accumulation mode. A gate-source voltage Vg polarises the 

dielectric, causing charge carriers to accumulate at the semiconductor-dielectric interface, with 

the source held grounded. A drain-source voltage Vd initiates a unidirectional flow of mobile 

charge carriers through the conducting channel, generating the drain-source current Id. Here, 

we demonstrate the operation principle of a p-type OFET where holes act as the majority charge 

carriers, and both Vg and Vd are negative to turn on the channel. In practice, a small, negative 

gate threshold voltage Vth is often necessary to fill up the charge carrier traps, allowing mobile 

holes to flow and contribute to the transistor current. This concept of threshold voltage in 

OFETs serves more as an empirical parameter for extrapolating the experimental Id–Vg 

relationship (transfer characteristics), rather than marking an onset voltage for the inversion 

regime as seen in MOSFETs. Nonetheless, achieving a near-zero threshold voltage which 

keeps stable under bias stressing or environmental exposure continues to be a crucial goal for 

reducing power dissipation and ensuring proper functionality in OFETs.  

 

Figure 2.6. Schematics of OFET structures and operation regimes. a, Four basic geometries in coplanar (top row) 

and staggered (second row) configurations. b, Conduction channel (dark grey area) for the linear regime (I), the 

onset of the saturation regime with pinch-off at the drain end (II), and full saturation regime (III). c, Corresponding 

output characteristics for each regime. 



Background and Theory   23 

 

  

A crucial basis for interpreting the current-voltage characteristics of OFETs based on 

Shockley’s model is the gradual channel approximation115, which posits that the vertical 

electric field is much greater than the lateral source-drain field. This assumption holds 

universally for OFETs with channel lengths L of a few tens to hundreds of microns and gate 

dielectrics several hundred nanometres thick.  Analytical treatment is then simplified to one-

dimensional analyses concerning the distribution of electric potential and current flow along 

the channel length.  The potential V(x) resultant from the source-drain field grows linearly from 

0 at the source (x = 0) to Vd at the drain end (x = L). Hence, the mobile charge carrier density 

at a position x away from the source is given by   mob i g thQ C V V V x    , where Ci is the 

gate dielectric capacitance per unit area (Fig. 2.6b and c, scenario Ⅰ). Neglecting diffusion, the 

drain current is determined by the Ohm’s law, provided that d g thV V V : 

  mob i g th

dV
I WQ F WC V V V x

dx
     ,                                 (2.10) 

where W is the channel width, µ is the charge carrier mobility (assumed independent of applied 

voltages), F = -dV/dx represents the source-drain electric field. Integrating the current with the 

boundary conditions of V(x) yields the linear-regime drain current as: 

  2
,

1

2d lin i lin g th d d

W
I C V V V V

L
      

,                                      (2.11) 

and the linear-regime mobility can be extracted from the transconductance /d gI V  . On the 

other hand, when d g thV V V  , charge carrier concentration at the drain end becomes zero, 

and the transistor is pinched-off at that location (Fig. 2.6b and c, scenario Ⅱ). As the magnitude 

of Vd continues to increase, this pinch-off point moves towards the source, resulting in a 

depletion region near the drain (Fig. 2.6b and c, scenario Ⅲ). Although drain current can still 

flow across the depletion zone, its magnitude becomes saturated as the current is determined 

by the fixed potential drop between the source and the pinch off point, given by Vg-Vth. In this 

saturation regime, the drain current is calculated by 



24  Background and Theory 

 

 2

, 2d sat i sat g th

W
I C V V

L
  .                                         (2.12) 

Consequently, the saturation-regime mobility can be determined from /d gI V  instead. The 

phenomenon of current saturation becomes evident in the FET output characteristics, when Id 

is plotted as a function of Vd for different fixed Vg (Fig. 2.6c).  

 

It is also convenient to plot the drain current against the gate voltage in a semilogarithmic 

manner to demonstrate the transfer characteristics (see Fig. 2.7). This approach facilitates a 

straightforward identification of the turn-on voltage Von, at which the drain current due to gate-

induced accumulation of charge carriers sets in. Moreover, it allows for the calculation of the 

on/off current ratio (the ratio of the saturation current at high Vg to the gate leakage current), 

which evaluates the device’s efficacy as a switching element in applications like actuators and 

logical circuits. The subthreshold swing, S, quantifies how fast the device transitions from the 

off-state to the on-state114, providing an overall measure of the density of traps Nin: 

 
2

10

ln10 1
log

g inB

id

V e Nk T
S

e CI

  
    

 .                                  (2.13) 

The theoretical lower limit of S at room temperature is about 60 mV/dec for a trap-free device, 

as the second term in the bracket approaches zero. An additional important metric for OFETs 

that still largely lags behind that of inorganic counterparts is the transit frequency, which 

indicates the maximum operational frequency for amplifying electrical signals116. We will not 

delve into this figure of merit throughout this thesis, as our focus is primarily on the DC 

electrical characterization.  

 



Background and Theory   25 

 

  

Figure 2.7. Extraction of main figures of merit for OFETs in the linear (a) and saturation (b) regimes. Reproduced 

from ref.117. 

 

2.2.2 Charge injection and contact resistance  

An indispensable assumption of the gradual channel model is that voltage drops at the contacts 

are negligible, allowing for charge injection/extraction through Ohmic contacts. However, 

sizeable contact resistance remains unavoidable and may significantly impact device 

performance, especially with the downscaling of channel dimensions and the increase in 

semiconductor conductivity. Optimal values for the channel width-normalized contact 

resistance, RcW, are of hundreds of Ω cm, and in some instances, are reported to be below 100 

Ω cm in several studies118–120. One intrinsic contribution to contact resistance arises from the 

interfacial injection barrier, which causes the injection current to grow nonlinearly with applied 

voltage. Essentially, charge carrier injection at a metal-semiconductor junction depends 

critically on the energetic mismatch between the Fermi levels of the two materials (Fig. 2.8a). 

When the metal and the OSC are brought into contact, an aligned Fermi level is established 

through charge exchange, creating a depletion region that extends into the OSC with a 

characteristic width Wd 114. According to the Schottky-Mott theory, in the absence of surface 

interactions, the Schottky barrier height Φb is calculated as the difference between the work 

function of the metal Φm and either the ionization potential Ip or the electron affinity χ of the 

semiconductor (equivalently the highest occupied molecular orbital, HOMO, or the lowest 

unoccupied molecular orbital, LUMO, of an OSC), depending on whether the injection of 



26  Background and Theory 

 

holes or electrons is being considered, i.e., ,pb p mI    and ,nb m    . However, this 

simplified model often proves inaccurate as it fails to account for many complex phenomena 

that can occur at the metal/OSC interface121 (Fig. 2.8b). These include the formation of an 

interfacial dipole, which causes an abrupt shift in the vacuum level across the junction; the 

presence of a high density of gap states due to defects, impurities or chemical reactions, which 

can facilitate hopping conduction or induce Fermi-level pinning; and the effect of image-force 

barrier lowering.  

 

Generally, two models are often quoted to describe the injection regimes from metals to 

crystalline semiconductors, governed by either thermionic emission or tunnelling 

mechanisms122–124 (Fig. 2.8c). On one hand, under moderate temperatures and electric fields, 

charges within the metal can acquire sufficient thermal energy to overcome the barrier into the 

semiconductor, resulting in a current density as described by the Richardson-Schottky model. 

On the other hand, if there are ample empty states near the contacts and the width of the 

depletion region is smaller than the mean free path of charges, charge carriers can tunnel 

through the barrier. The tunnelling mechanism is applicable at relatively low temperatures and 

converges to the Fowler-Nordheim formalism at high electric fields. However, in organic 

semiconductors that are prone to disorder, the mean free path of charge carriers – usually on 

the order of intermolecular distances – tends to be much smaller than the width of the depletion 

region. Therefore, extra processes such as the diffusion of charge carriers towards the bulk 

semiconductor and the recombination of back-scattered carriers with their image charges are 

also important for any comprehensive microscopic model of charge injection into molecular 

semiconductors123,125.  

 



Background and Theory   27 

 

  

 

Figure 2.8. Charge injection at the metal/organic semiconductor interface. a, Formation of the Schottky barrier 

ΦBp due to the energetic mismatch between the work function of gold EF and that of an intrinsic p-type OSC EFi. 

eVbi denotes the built-in potential. b, Depiction of an interfacial dipole and gap states (left), and the image-force 

barrier lowering (right). c, Charge injection mechanisms illustrated for thermionic emission (left) and tunnelling 

(right). d, Equivalent circuit diagrams for charge injection in coplanar (left) and staggered (right) OFETs, with 

interfacial and bulk contributions to the contact resistance noted with respective subscripts. Adapted and 

reproduced from ref.121,124,126. 

 

Another key source of contact resistance in OFETs, particularly in staggered devices, stems 

from the bulk resistance associated with charge transport through the thickness of the 

semiconductor beneath the contacts towards the channel (see Fig. 2.8d for the equivalent circuit 

diagrams of two types of contact configurations). The precise injection area is determined by 

the relative magnitudes of the channel resistance and the contact resistivity; when the former 

is predominant, injection tends to occur over a narrow region near the edge of contacts rather 

than across the entire area overlapping with the gate. This phenomenon is known as current 

crowding127,128. In this sense, semiconductor thin films consisting of fewer molecular layers 

are preferred, as they effectively minimise the access resistance and promote the formation of 

Ohmic-like contacts in staggered OFETs129,130.  

 



28  Background and Theory 

 

Regardless of the exact device geometry, the total resistance (Rtot) of an OFET can generally 

be decomposed into a channel resistance (Rch) and contact resistances pertinent to the source 

and drain electrodes (Rs and Rd, respectively). Assuming that the OSC layer is uniform and that 

Rch scales linearly with the channel length while the contact resistance remains unchanged, 

evaluating the total resistances (usually normalized by the channel width for cross-literature 

comparison) across a series of devices with varying channel lengths at the same effective gate 

voltage facilitates a linear extrapolation to the y-intercept, which signifies the contact resistance 

(Fig. 2.9a). This transmission-line (or transfer-length) method can be modified to accommodate 

significant parameter variations from one device to another, i.e. by plotting RtotW/L against 1/L 

and extracting the slope, which is expected to be RcW 131. An alternative method that can 

differentiate the individual contributions of Rs and Rd to the overall contact resistance is the 

gated four-point-probe (gFPP) measurement (Fig. 2.9b). This approach involves two additional 

voltage probes within the channel, positioned between the source and drain contacts at 

locations L1 and L2 (where x = 0 marks the edge of the source). In this configuration, the actual 

potential drop across the channel in the linear regime of FET operation is given by 

2 1

2 1
ch

V V
V L

L L


 


,                                                      (2.14) 

where V1 and V2 are the measured potentials by the respective voltage probes. By linearly 

extrapolating the channel potential profile towards the source and drain contacts, expressions 

for the voltage drops at these two locations can be derived as: 

2 1
1 1

2 1
s

V V
V V L

L L


  


,                                              (2.15a) 

 2 1
2 2

2 1
d d

V V
V V V L L

L L

 
      

.                                    (2,15b) 

Hence, the contact resistance at source or drain is obtained by dividing the associated voltage 

drop by the drain current. The gFPP method also enables the extraction of linear-regime charge 

mobility free from contact effects, as the four-probe channel conductivity can be written 

explicitly as: 



Background and Theory   29 

 

  

 4 4
4

d
p i g th p

p

I D
C V V

V W
    ,                                       (2.16)  

where D = L2 - L1, V4p = V1 - V2, and µ4p represents the four-probe mobility. Ideally, the voltage 

sensing probes should be point-like to minimise disturbance of the surrounding electric field. 

However, if their widths are substantial due to fabrication limitations, an attenuated voltage 

drop occurs immediately adjacent to the equipotential edges of the probes, whereas a stronger 

electric field develops in other parts of the channel132. This longitudinal channel shunting effect 

should be corrected to avoid overestimating the four-probe mobilities. 

 

Quantitative analysis of contact resistance in OFETs can also be performed alternatively. For 

instance, the Y function method assumes a mobility attenuation factor that includes 

contributions from contact resistance133,134. Additionally, impedance spectroscopy can be 

applied alongside an appropriate equivalent circuit model to dissect the resistance 

characteristics135,136. Another potent technique for direct observation of potential drops across 

contact/semiconductor interfaces in bottom-gated devices is Kelvin probe force microscopy 

(KPFM). We will delve into this method in greater detail in the next chapter. In light of the 

considerable contact resistance observed in OFETs, several efficacious strategies can be 

employed to mitigate its effects. These include selecting proper metals for work function 

matching120,137 (refer to Fig. 2.9c for a library of work functions of common electrode 

materials), introducing molecular dipoles from self-assembly monolayers (SAMs) to modify 

local electric fields (e.g., a thiol-based SAM can bond covalently with Au)138,139, and 

incorporating an insertion layer of metal oxides, inorganic salts or organic compounds to tune 

the work function or enable contact doping140,141 (Fig. 2.9d). Besides, other electrode materials 

such as charge-transfer complexes, carbon nanotubes, graphene and its derivatives are 

increasingly gaining attention due to their compatibility with flexible, transparent and 

thermally stable applications124,126.  

 



30  Background and Theory 

 

 

Figure 2.9. Schematics of the transmission-line method (a) and gated four-point-probe measurement (b) for 

evaluating contact resistance in OFETs. c, Metal work functions of conductive materials used as electrodes 

(middle), along with the electron affinity (top) and ionization energy (bottom) of insulating materials used as 

dielectrics in OTFTs. d, Illustration of how contact doping modifies the depletion region and influences injection 

mechanisms. Adapted and reproduced from ref.140,142–144. 

 

2.2.3 Nonideal behaviours in OFETs 

As inferred from our previous discussion, large contact resistance in OFETs causes deviations 

in the current-voltage characteristics from the ideal gradual channel model. The deviation 

might manifest as a “kink” on the transfer curve (Fig. 2.10a), where the low-voltage region 

exhibits a much steeper slope compared to the high |Vg| region136,145,146. Consequently, it could 

lead to overestimated mobility values if linear fitting is applied to the steeper portion. This kink 

feature emerges when contact resistance dominates in the low-gate bias region and decreases 

rapidly as it becomes overwhelmed by channel resistance at higher carrier concentrations. Such 

pronounced Vg dependence of Rc can be expected in a gated Schottky contact, where the mode 

of charge injection transitions relatively abruptly from thermionic emission to thermionic-field 

emission and, eventually, to tunnelling processes136. Liu et al. systematically studied the effects 



Background and Theory   31 

 

  

of non-Ohmic contacts on the over- or under-estimation of mobility, in the context of gated 

Schottky or resistive contacts145 (Fig. 2.10a). They highlighted that the kink feature, indicated 

by the red curves in Fig. 2.10a, is not the sole indicator of significant contact resistance; 

additionally, when the voltage drop across the injection barrier is predominant, the channel 

may initially operate in a Schottky barrier transistor mode and only transitions to the normal 

transistor mode after reaching a certain level of gate bias.  

 

Nonideal OFET characteristics can arise from factors beyond contact-limited currents at the 

metal-semiconductor interface147–149. For instance, a carrier concentration-dependent mobility 

can be observed as a result of charge trapping at localized tail states of OSCs150,151. As the gate 

bias increases, the Fermi level resides closer to the transport level and more trap states are filled, 

resulting in charge conduction that is less susceptible to trapping, thereby enhancing mobility. 

Consequently, the transfer curves transform from straight lines into curves with an upward 

curvature (Fig. 2.10b, left). They also exhibit a large subthreshold region, indicative of slow 

trap filling upon the formation of a conductive channel. Nonuniform trapping of electrons, 

which are the minority charge carriers in p-type devices, has been identified as a potential cause 

for the double slope phenomenon (Fig. 2.10b, right) – a steep slope at low Vg but a shallow 

slope at high Vg – in the transfer curves of some low-bandgap donor-acceptor polymer thin film 

transistors152,153. Research has also illuminated that an alternative cause of the double-slope 

nonideality is the higher degree of disorder at the interface compared to the bulk. At high gate 

voltages where charges are more strongly attracted toward the interface, the increased 

interfacial disorder results in lower mobility154. The OSC/dielectric interface is observed to 

play critical roles in determining the ideality of OFET behaviours. Un et al. performed scanning 

Kelvin probe microscopy with gate bias stressing and revealed the universal trapping of holes 

or electrons by the active functional groups on various dielectrics in the presence of adsorbed 

water155. Their observations support a semiconductor-unrelated trapping mechanism 

responsible for suppressed drain currents at high gate voltages. In addition, a quasi-1D transport 

mechanism in molecular crystals or highly oriented polymers has been proposed to explain the 

downward bending of transfer curves in bottom-gate, top-contact devices156 (Fig. 2.10b, 



32  Background and Theory 

 

middle). According to this model, increasing the gate voltage pulls mobile charge carriers 

closer to the channel, which in turn diminishes the proportion of bulk transport and heightens 

the difficulty in charge collection at the drain contact. To sum up, it is reasonable that multiple 

mechanisms could simultaneously contribute to the nonlinear transfer characteristics of OFETs. 

Lastly, as our focus has primarily been on measurements taken at a fixed drain voltage, we 

have not explored variations in extracted mobility with the electric field parallel to the 

conduction channel, such as those predicted by the Poole-Frenkel model157.  

 

Figure 2.10. a, Deviations from linear transfer characteristics due to contact resistance: gate voltage dependence 

of resistances (left), source-drain current (middle), and extracted mobility (right). b, Examples of nonideal transfer 

curves showcasing an upward curvature (left), downward curvature (middle), and double slope (right). The 

reliability factor r is calculated as the percentage ratio of the slopes between the blue and red dashed lines. Adapted 

and reproduced from ref. 145,148,151. 

 

Extensive efforts have been devoted to resolving the mobility hype in past literature, where 

overestimated mobilities were reported despite noticeable nonideal transfer curves. A 

reliability factor r has been proposed to assess whether the behaviour of transfer characteristics 

adheres to a linear increase of conductivity with carrier density under the assumptions of a 

constant mobility and negligible threshold voltage158. It is defined as the ratio of the maximum 



Background and Theory   33 

 

  

channel conductivity experimentally achieved in a FET at the maximum gate voltage to that in 

an ideally functioning FET with the claimed mobility and identical device parameters at the 

same maximum |Vg|.  Additional guidelines for reporting high-performance OFETs are also 

elucidated in this commentary article, which we will largely follow in our analysis throughout 

this thesis. In a nutshell, emphasizing and examining the origins of nonidealities in OFETs are 

crucial for accurately assessing the performance metrics and guiding future research directions 

towards reliable applications in organic electronics. 

 

To conclude this section on device physics, we present a complete view of the energy band 

diagrams for a p-type OFET employing Au electrodes and the SiO2 dielectric. The gate-source 

and drain-source configurations are depicted correspondingly in Fig. 2.11. It is critical to bear 

in mind that peculiar phenomena observed during electrical characterizations may result from 

combined effects of multiple device components. Therefore, maintaining a holistic view is 

essential when studying the charge transport properties in organic field-effect transistors.  

 

 

Figure 2.11. Energy band diagrams for a p-type OFET: the gate-source side (a) and the drain-source side (b). 

Adapted and reproduced from ref. 159. 

 

 



34  Background and Theory 

 

 



 

Chapter 3 Experimental Methods 

3.1 Solution-processed thin film deposition 

The amenability to solution processing renders organic semiconductors promising for facile 

and scalable production of thin film-based devices, pivotal in advancing both fundamental 

research and real-life applications. Methods prevalently employed in academic research 

include drop casting, in which the desired OSC precipitates from the evaporating solvent and 

recrystallized on a solid substrate in a quasi-equilibrium process; and spin coating which 

utilizes the centrifugal action at high rotational speeds to rapidly disperse the material and form 

a homogeneous film. Despite the efficacy of these techniques, which have been tailored 

through specific modifications for fabricating high performance samples35,160–162, issues such 

as incomplete surface coverage and significant material wastage impede the large-area, high 

throughput manufacture of organic electronic devices. Moreover, it is usually difficult to 

control the crystal nucleation and growth within these stochastic coating processes, making it 

challenging to manage the resultant film morphology. In response to these challenges, 

meniscus-guided coating (MGC) techniques emerge as a distinct solution which takes 

advantage of the guided movement of the liquid meniscus and facilitates the molecular 

assembly into more ordered structures. Depending on the way of solution supply and the 

geometry of the coating head, MGC methods can be classified into dip coating, zone casting, 

blade coating, solution shearing, and slot die coating, among others (Fig. 3.1a), whereas the 

underlying physical mechanism governing the fluid dynamics and film deposition remains 

alike. Hence, we will use the terms ‘meniscus-guided coating’, ‘blade coating’ or ‘solution 

shearing’ interchangeably in the ensuing discussion.  



36  Experimental Methods 

 

Figure 3.1. Meniscus-guided coating of OSC thin films. a, Schematic of typical meniscus-guided coating 

techniques. b, Two primary deposition regimes at low (evaporation) and high (Landau-Levich) coating speeds. c, 

Measured solid film thickness as a function of coating speed. Adapted and modified from ref.163,164. 

 

Generally, two fluid mechanical regimes (Fig. 3.1b) can be identified with the MGC deposition, 

each characterized by its unique relationship between film thickness and coating speed (Fig. 

3.1c)164,165. At low deposition velocities, solvent evaporation at the meniscus occurs on a 

comparable timescale to that of solid film growth, such that the film drying process is directly 

impacted by the meniscus, the internal fluid flow field, and any applied shear forces. A 

characteristic inverse relationship between the dry film thickness and the coating speed is 

expected in this evaporation regime. As the coating speed increases, viscous effects start to 

play a role and eventually dominate at high capillary numbers. A wet film is first pulled out 

before solvent evaporation and the film drying kinetics are decoupled from the primary effects 

of the coating mechanism. In contrast, the deposited film thickness scales positively with the 

coating speed in the Landau-Levich regime. The transitional coating speed demarcating these 

two regimes depends on several factors including solution concentration, liquid viscosity, and 

substrate temperature. In our experimental practice employing dilute OSC solutions in typical 

aromatic solvents at relatively low temperatures, this transition takes place at speeds on the 



Experimental Methods                                                                                                           37 

 

  

order of millimetres per second. We have opted for the slower evaporative regime due to its 

suitability for depositing layered two-dimensional thin films with large crystalline domains, 

and the clearer correlation between coating parameters and resultant film morphologies. 

 

Tuning the interplay between the coating speed and the solvent evaporation rate is crucial to 

control the size, shape anisotropy, and uniformity of crystalline domains in MGC166–169. 

Traditional crystallization theory conceptualizes OSC deposition from solution as a two-step 

process, encompassing nucleation followed by crystal growth. Heterogeneous nucleation with 

a low density of nuclei is favoured over homogeneous nucleation which would result in a 

random distribution of nucleation sites, sizes and orientations. If the coating speed is too fast, 

solvent evaporation drives the solute concentration quickly beyond the critical supersaturation, 

giving rise to spontaneous and sporadic nucleation (see the inset of Fig. 3.2a). Conversely, 

under slow coating conditions, solute depletion from solution due to crystallization dominates 

and promotes aligned morphology in the presence of directional convective flow along the 

coating direction. It has been surmised that slow processing at the equilibrium front evaporation 

speed of the chosen solvent leads to optimized morphology and superior charge transport 

characteristics in MSC-based OTFTs170. In recent years, considerable efforts have been 

directed towards developing analytical models that elucidate the relationship between coating 

parameters (coating speed, temperature, solution concentration, physical properties of solvents, 

etc.) and provide empirical guidelines to supplant labour-intensive trial-and-error 

experiments170–172. For instance, Chen et al. examined the morphology of C8-BTBT films under 

varying solution shearing conditions and formulated a concise equation to delineate the roles 

of individual processing parameters171: 

vap bS T

RT
osc osc

dm d
avt c e

dt dt





    (3.1) 

Here, dm/dt is the mass transfer rate, osc is the OSC density, a is the substrate width, v is the 

shearing speed, osct  is the effective thickness of the film, c is the solution concentration, d dt



38  Experimental Methods 

 

is the instantaneous solvent evaporation rate which correlates to the entropy change of 

vaporization ΔSvap, the deposition temperature T, and the solvent boiling point Tb in an 

Arrhenius form, and R is the universal gas constant. Despite the success in predicting the 

optimal processing windows for highly crystalline OSC thin films in certain implementations, 

the MGC process involves a multitude of physical processes173–175 (e.g. stick-slip motion of the 

contact line, fingering instability, and Marangoni flow induced by temperature or concentration 

gradients.) which dramatically impact the eventual morphology and vary in practice (Fig. 3.2a). 

Hence, it warrants further research to clarify the complex fluid dynamics and thermodynamics 

to adapt MGC to diverse material systems and form factors. 

 

 

Figure 3.2. a, Schematic of flows, gradients and molecular behaviour associated with the meniscus. The inset 

highlights the critical supersaturation curve and the metastable zone of a supersaturated OSC solution within a 

concentration-temperature phase diagram. Adapted and modified from ref.176,177. b, Close-up view of our home-

made blade coater, captured with a smartphone camera. Depending on the processing parameters and the surface 

roughness, blade-coated Ph-BTBT-C10 samples on SiO2/Si substrates can exhibit single-crystalline (c), 

polycrystalline (d), and two-dimensional mesoscopically aggregated structures (e), each characterized by atomic 

force microscopy. 

 



Experimental Methods                                                                                                           39 

 

  

Throughout this thesis, polycrystalline thin films of Ph-BTBT-C10 were prepared using blade 

coating with our customized-built blade coater in a nitrogen glovebox (Fig. 3.2b). Ph-BTBT-

C10 was sourced from TCI Chemicals and used without further purification, due to the absence 

of an adequate sublimation setup and the requisite expertise. This commercially available 

product is designated as HPLC grade, with a purity of over 99.5%, ensuring that the impact of 

inherent impurities is negligible. The raw material was dissolved in 1,2-dichlorobenzene 

(Thermo Scientific Chemicals) at 80℃ with a concentration of 8 mg mL-1. The substrate was 

preheated at the same temperature by a hotplate mounted on a moving stage, which was 

controlled by a benchtop stepper motor (Thorlabs, BSC201). Approximately 50 µL of 

preheated OSC solution was then carefully injected into the narrow gap (~ 200 µm) between 

the substrate surface and the polytetrafluoroethylene (PTFE) blade. The substrate was 

consistently pulled out at a constant speed of 0.14 mm s-1 to deposit a continuous thin film. 

Any residual solvent was eliminated by leaving the substrate on the heated stage for another 2-

3 minutes following the coating process. In the fabrication of single-crystalline thin films, we 

adopted either blade coating or drop casting for the ease of sample preparation. Chlorobenzene 

(Thermo Scientific Chemicals) was selected as the solvent for blade coating at 40℃ due to its 

higher volatility than dichlorobenzene, and a low concentration of ~1 mg mL-1 combined with 

an ultralow coating speed of 3 µm s-1 yielded 2-3 molecular bilayer-thick, millimetre-wide 

crystalline domains free from thermal cracks. In the drop casting approach, a droplet of 4 mg 

mL-1 xylene (mixed, Thermo Scientific Chemicals) solution of Ph-BTBT-C10, preheated at 

100℃, was cast onto a clean substrate and allowed to dry naturally under ambient conditions. 

Subsequent to the slow crystallization, these samples were placed in a vacuum oven overnight 

to remove solvent residue. 

 

We have implemented all recommended measures to minimize processing-induced 

contamination, as advised by our senior colleagues178. These precautions include avoiding 

volatile or reactive chemicals commonly found in inert atmosphere gloveboxes, as well as 

substances that leach from laboratory consumables. Best practices such as maintaining a well-

conditioned solvent trap, thoroughly purging the glovebox, and replacing plastic 



40  Experimental Methods 

 

pipettes/syringes and siliconized needles are crucial. By adhering to these protocols, we ensure 

a clean fabrication process and enhance the reliability of solution-processable organic 

semiconductor devices. 

 

3.2 Device fabrication 

In the fabrication of organic thin film transistors, heavily doped silicon wafers with a 300 nm-

thick thermally grown oxide layer were used as substrates. They were sequentially rinsed and 

sonicated in deionized water (DI water), acetone, and 2-propanol (IPA), each for 10 minutes. 

The substrates were dried using nitrogen and further treated with oxygen plasma for 10 minutes. 

Ph-BTBT-C10 was deposited onto the prepared substrates via blade coating or drop casting, as 

detailed in Chapter 3.1. For top-contact devices (Fig. 3.3a), 25 nm-thick Au electrodes were 

deposited by thermal evaporation through a shadow mask (Fig. 3.3c, upper) at a rate of 0.3 Å 

s-1 under a high vacuum of 10-6 mbar. To mitigate the effects of fringe currents in electrical 

characterizations, the semiconductor film outside the channel region was meticulously 

removed using a cocktail stick and a probe tip, or etched away using a laser (OPTEC ProMaster, 

248 nm KrF), thereby refining the active device area.  

 

On the other hand, the electrodes of bottom-contact devices (Fig. 3.3b) were either defined 

using the same shadow mask evaporation or pre-patterned via photolithography with an 

interdigitated configuration (Fig. 3.3c, lower), prior to OSC deposition. Bilayer photoresist 

LOR5B (Kayaku Advanced Materials, Inc.) and S1813 (SHIPLEY, MICROPOSIT) were spin-

cast at 5000 rpm for 30 seconds and subsequently subjected to hotplate baking at 180℃ and 

120℃ for 5 minutes and 2 minutes, respectively. After a UV light exposure of ~ 12 seconds 

using a mask aligner, the samples were developed in MF319 (SHIPLEY, MICROPOSIT) with 

gentle agitation, followed by a rinse in DI water and drying with nitrogen. An optional brief 

oxygen plasma treatment was employed to clean any leftover of photoresist on the exposed 

substrate surface. An additional layer of Cr (3 nm) was thermally deposited first to promote the 



Experimental Methods                                                                                                           41 

 

  

adhesion of Au (15 nm) to SiO2. The lift-off process involved soaking the samples in 1-Methyl-

2-pyrrolidinone (NMP) overnight, followed by a sequential solvent rinse for cleaning. In order 

to improve charge injection at the metal-semiconductor interface, a pentafluorobenzenethiol 

(PFBT) self-assembled monolayer (SAM) treatment on the bottom-contact source/drain 

electrodes was applied by immersing the substrates in a 30 mM PFBT solution in 2-propanol 

for 20 min, followed by solvent cleaning with pure IPA. It is noteworthy to mention that 

previous reports by Iino et al. have indicated that the same material, when processed through 

simple spin coating and thermal annealing, can result in a field-effect mobility exceeding 10 

cm2 V-1 s-1 30,179. However, such high performance proved elusive in our spin-cast bottom-gate, 

bottom-contact transistors (refer to Fig. A1.1 in the Appendix for more details). The average 

saturation mobility we observed was slightly above 2 cm2 V-1 s-1, and the discrepancy might 

arise from a lack of additional purification processes on the OSC material we purchased, or it 

could be associated with a higher density of defects or grain boundaries linked to the longer 

channel lengths utilized in our device configurations. 

 

Device engineering on OFETs, as will be detailed in Chapter 5, encompasses various strategies, 

including SAM treatment of dielectric surfaces (Fig. 3.3a, middle), contact modification in the 

top-contact architecture (Fig. 3.3a, lower), and electrode transfer onto blade-coated 

polycrystalline OSC films (Fig. 3.3d).  Phenyltrichlorosilane (PTS) proved to be effective for 

passivating surface hydroxyl groups that act as charge carrier traps, and for ensuring 

appropriate wetting properties for solution coating180. This approach contrasts with the use of 

octadecyltrichlorosilane (ODTS)-modified SiO2 surfaces, which exhibit high hydrophobicity 

and impede proper film growth of Ph-BTBT-C10 via blade coating. The substrates were 

immersed in a 3 wt% PTS solution in toluene (Sigma-Aldrich) and maintained at 90℃ for over 

15 hours. They were briefly sonicated in toluene post-immersion, gently wiped with a foam 

swab, and sequentially rinsed with toluene, acetone and IPA. Surface coverage of PTS was 

indicated from a noticeable reduction of the water contact angle as compared to untreated SiO2; 

however, the exact molecular order and packing density of the SAM is difficult to assess 

without sophisticated X-ray or vibrational spectroscopy measurement181–183. Contact 



42  Experimental Methods 

 

engineering in bottom-gate, top-contact OFETs was accomplished by inserting a thermally 

evaporated buffer layer (~5 nm) of either molybdenum oxide (MoOx) or 2,3,5,6-Tetrafluoro-

7,7,8,8-tetracyanoquinodimethane (F4-TCNQ) between the OSC and the top Au layer. MoOx 

has a deep work function and can alleviate contact resistance in p-type staggered organic 

transistors when used as a thin interlayer184–186. F4-TCNQ, a p-type small molecule dopant, is 

utilized for contact doping to reduce the thickness of the depletion region, facilitate charge 

carrier tunnelling at the metal/OSC interface, and fill the in-gap trap states in the vertical access 

regions118,187,188. To fabricate top-contact OFETs with transferred electrodes, we followed a 

previously reported wet processing approach189. Gold source/drain electrodes were initially 

deposited onto a hydrophobic substrate treated with ODTS via vapour deposition at elevated 

temperatures. A protection layer of poly(methyl methacrylate) (PMMA, Mw ~ 15000, Sigma-

Aldrich) was spin-cast from a 3 wt% butyl acetate solution and annealed on a hot plate. Then, 

an aqueous solution of poly(vinyl alcohol) (PVA, 86.7-88.7 mol% hydrolysis, Sigma-Aldrich) 

was spin-cast on top of PMMA with subsequent baking to remove residual water. The hybrid 

film of PVA/PMMA/Au was peeled off using Scotch tape and laminated onto the 

polycrystalline thin film with a mild heating at 80℃ for enhanced adhesion. The final steps 

included complete dissolution of PVA in DI water, nitrogen drying, and thermal annealing. 

Alternatively, for achieving a damage-free metal/OSC interface suitable for scanning probe 

microscopy characterization, a thick (~300 nm) flake of thermally evaporated Au was lifted 

and transferred using a probe tip and a sharp tweezer. 

 



Experimental Methods                                                                                                           43 

 

  

 

Figure 3.3. Schematics of bottom-gate, top-contact (a) and bottom-contact (b) Ph-BTBT-C10 thin-film transistors. 

Dimensions depicted are not to scale. PTS modification of the SiO2 surface and the insertion of an interlayer of 

MoOx or F4-TCNQ for Au contact engineering are displayed in the middle and lower panel in a. The inset shows 

the molecular structures of the respective organic materials. c, Optical micrograph of the source/drain electrode 

patterns in the shadow mask (upper) and the photomask (lower). d, Direct exfoliation and transfer of Au electrodes 

onto OSC films. Adapted and modified from ref.189.     

 

3.3 Electrical characterization 

Room temperature FET and stress characteristics were measured in a nitrogen atmosphere (O2 

and H2O < 5 ppm) using an Agilent 4155B Semiconductor Parameter Analyzer (SPA), under 

room illumination with the microscope light turned off. To minimize gate bias-stress instability 

induced by transfer sweeps, we chose a short integration time of 960 µs, and set the current 

measurement ranges to 10 µA Limited auto ranging for a compromise between sweep speed 

and current measurement resolution. Here, 10 µA Limited auto ranging uses the 10 µA range 

to measure 1 nA, and achieves a resolution of 100 pA at the specified integration time. 



44  Experimental Methods 

 

Adhering to this measurement protocol leads to a negligible shift of transfer curves after 10 

fast forward sweep cycles. To assess the bias-stress stability of OFETs, devices were subjected 

to a continuous negative gate stress for a set duration while the source and drain electrodes 

were grounded. Following the removal of the stress gate voltage, a transfer curve was 

immediately acquired based on the abovementioned settings, succeeded by another stress step. 

The interval between successive stress and sweep events was limited to just 2-3 seconds, thus 

we do not expect any significant device recovery to occur during these brief transition periods. 

 

For low-temperature FET characterization, samples were loaded into a Desert Cryogenics 

TTP4 probe station and the chamber was evacuated to a high vacuum of ~10-5 mbar. Liquid 

nitrogen was supplied from a dewar with a controlled flow rate to cool the sample stage, while 

a heating power applied via a Lakeshore 331S temperature controller was used to maintain the 

set temperature. The measurement range spanned from 80 K to 300 K, with each temperature 

being held steady for above 20 minutes prior to characterization to ensure thermal equilibrium 

between the chamber and the samples.  By sequentially increasing the temperature, we were 

able to probe the intrinsic low-temperature properties without inducing much bias stress 

degradation. To investigate charge transport properties of Ph-BTBT-C10 at elevated 

temperature, the sample was mounted into a sub-miniature probe system (MPS-PTH, 

NEXTRON) featuring a Peltier element and an active cooling system.  This chamber was then 

transferred to a nitrogen glovebox and hermetically sealed. To ensure a more stable inert 

atmosphere, the juncture where the chamber lid meets was additionally sealed with parafilm. 

A Keithley 4200A-SCS parameter analyser was connected to the microprobes to record the 

FET characteristics. Temperature adjustment was performed gradually at a slow rate of 

2℃/min using a NEXTRON NC-T temperature controller, and each temperature was 

maintained for at least 10 minutes to stabilize before commencing measurements.  

 

Field-effect mobilities were extracted using a linear regression fit on the forward sweep of the 

transfer curves, following the standard Shockley equations for both the linear and saturation 

regimes: 



Experimental Methods                                                                                                           45 

 

  

 

lin,2p

4

lin,4p

,d

i d g

d p

i g

IL

WCV V

I VD

WC V





 
    

 
 
  

 (3.2a) 

2

sat,2p

2 d

i g

IL

WC V


 
 
  

 (3.2b) 

where the parameters are defined as per the discussion in Chapter 2. The threshold voltages 

were determined through linear extrapolation across an extended linear range of the ( )d gI V  or 

( )
d gI V curves.  In addition, the specific voltage beyond which the source-drain current 

exhibits a dramatic increase – surpassing the gate leakage current (typically in the range of a 

few nanoamperes) by several orders of magnitude – was identified as the turn-on voltage. 

 

Another suggested technique to confirm the reported high field-effect mobility and explore the 

nuances of transport physics in molecular semiconductors is the Hall effect measurement. 

Unfortunately, due to prolonged technical issues with our equipment and limited laboratory 

time, we were unable to perform temperature-dependent Hall measurements in Chapter 4. 

Although the four-point-probe device configuration (Fig. 3.3c, upper panel) can readily be 

adapted for Hall measurements, we meticulously patterned the semiconductor layer and 

manually bonded fragile metal electrodes onto designated PCB chip terminals using thin 

copper wires. Another concern involves bias stress stability, as continuous gate bias is 

necessary to maintain sufficient conductivity across the channel for a well-resolved Hall signal. 

Overcoming these challenges is crucial for future Hall effect characterization to deepen our 

understanding of charge transport in Ph-BTBT-C10 thin films. 



46  Experimental Methods 

 

3.4 Scanning probe microscopy 

Scanning probe microscopy comprises a large family of techniques that involve raster-scanning 

a sharp probe over a sample surface to interrogate specific material properties, yielding real-

space images at nanoscale or even atomic resolution190. One prominent method within this 

category, extensively applied for topographic imaging, is atomic force microscopy (AFM)191,192. 

In AFM, a sharp probe tip is affixed to the free end of a microfabricated cantilever beam, and 

the deflection of the cantilever is measured by capturing a reflected laser beam off the vertex 

with a position-sensitive photodiode detector. In the typical tapping mode, or amplitude-

modulation mode, the cantilever is driven by a piezoelectric actuator to vibrate near its resonant 

frequency, and its oscillation amplitude and phase shift are detected through a lock-in amplifier. 

As the probe tip approaches and intermittently contacts the sample surface during each 

oscillation cycle, it senses van der Waals-type interactions with the sample (or more generally, 

longer-range attractive and short-range repulsive forces), resulting in changes in the resonant 

frequency and, consequently, the oscillation amplitude relative to the tip-sample distance. 

While a certain amplitude setpoint is defined, the feedback loop adjusts the tip-sample distance 

with the z-piezo to maintain the preset oscillation amplitude. Hence, the resulting z-piezo 

movements generate surface topography as the tip scans laterally in the xy plane. In addition 

to providing height information, simultaneous phase imaging offers insights into energy 

dissipation during the oscillation cycles, revealing variations in stiffness or adhesion193,194. 

 



Experimental Methods                                                                                                           47 

 

  

Figure 3.4. a, Electronic energy levels of a sample and a conducting AFM tip: (a) when separated by a distance 

d; (b) upon electrical contact, showing an offset in the vacuum level VCPD; and (c) with an external bias VDC applied 

to nullify the contact potential difference. b, Schematic of KPFM measurement performed using Asylum Research 

AFMs. c, Topographic view (a) and cross-sectional surface potential profile at various gate voltages (b) and re-

measured immediately after the gate biasing (c). Adapted from ref.195–197. 

 

Apart from assessing surface topography, determining the electrical surface properties across 

various materials holds importance in the study of organic electronics as well. Kelvin probe 

force microscopy (KPFM), also known as scanning Kelvin probe microscopy (SKPM) is a 

conducting-AFM based technique that provides quantitative results of the local surface 

potential distribution of a sample195,198. The term “Kelvin probe” originates from a non-contact 

vibrating parallel-plate capacitor device invented by Lord Kelvin, which was designed for 

macroscopic measurement of work function or surface potential199. The adaptation of this 

concept to scanning probe microscopy was pioneered by Nonnenmacher et al. in 1991200. The 

fundamental principle of KPFM revolves around the interaction between a conducting AFM 

tip and a sample possessing different work functions. When the tip and sample are brought into 

electrical contact, Fermi level alignment induces current tunnelling and results in an offset in 



48  Experimental Methods 

 

their vacuum levels, which is equivalent to the contact potential difference (CPD) between the 

two materials, denoted as VCPD in Fig. 3.4a. The resultant electrostatic force Fes is given by 

     21
,

2es

dC z
F z V

dz
                                                  (3.3) 

where dC dz is the gradient of the capacitance between the tip and sample, and V is the 

potential difference. In KPFM, an AC voltage VAC of angular frequency   that generates 

oscillating electrical forces between the probe tip and sample surface, along with a nullifying 

DC bias VDC are superimposed to the AFM tip (Fig. 3.4b), so that 

 sin .AC DC CPDV V t V V                                            (3.4) 

Substituting Eq. (3.4) back to Eq. (3.3) gives the complete form of the electrostatic force acting 

on the tip, which comprises a DC component DCF  implying a static deflection of the probe, a 

component F with angular frequency  , and a component 2F  with frequency 2  useful for 

capacitance microscopy: 

   21

2DC DC CPD

C z
F V V

z

       
 

     sinDC CPD AC

C z
F V V V t

z 


  


 

   2
2

1
cos 2 1 .

4 AC

C z
F V t

z 


   
                                       (3.5) 

By minimising the F  component through a feedback loop, the local CPD can be directly 

determined by monitoring VDC, and the work function or surface potential of the sample can be 

inferred, provided that the work function of the AFM tip is calibrated with a reference material. 

 

The derivation presented, which draws parallel to Lord Kelvin’s initial proposal of two parallel 

metal plates, is particularly valid for mapping the surface potential of metallic surfaces. 



Experimental Methods                                                                                                           49 

 

  

Extending the theoretical framework to more intricate systems necessitates a deeper analysis 

incorporating additional contributors to the potential difference such as the space-charge layer 

and the presence of trapped charges. The application of KPFM to organic semiconductors has 

flourished over the past few decades, providing a non-invasive means to explore the effect of 

microstructure on charge transport201,202, the potentiometry of organic electronic devices203–205, 

and the origins of charge carrier traps and injection barriers197,206,207. To illustrate with an 

example, Figure 3.4c depicts a KPFM study by Tello, Chiesa, and their colleagues on ultrathin-

film pentacene transistors where a clear correlation between film morphology and surface 

potential profile is observed197. Within thin intergrain regions insufficient molecular coverage 

fails to support the formation of a complete accumulation layer, and the applied negative gate 

voltage is not fully screened. Repeated surface potential measurement immediately after 

removing the gate bias uncovers a positive surface potential in these regions, suggesting that 

hole trapping preferentially occurs in between thicker pentacene grains. 

 

We employed these microscopic imaging techniques in conjunction with gate biasing tests or 

temperature variations to elucidate the trapping dynamics of charge carriers and morphological 

transformations within molecular assemblies. The KPFM approach provides crucial evidence 

on the subtle variations in molecular orientations and the evolution of packing disorder. 

Throughout this thesis, tapping mode AFM measurements were conducted using either an 

Asylum Research MFP-3D or a Cypher ES system. Two types of probes were used: RTESPA-

150 (resonant frequency 150 kHz, spring constant 5 N m-1, Bruker) and AC240TS-R3 (resonant 

frequency 70 kHz, spring constant 2 N m-1, Oxford Instruments). The measurements were 

performed at a scan rate of 1 Hz with 512 samples per line. KPFM was expertly conducted by 

Dr. Xinkai Qiu on the Cypher ES system, employing a SCM-PIT V2 probe (resonant frequency 

75 kHz, spring constant 4 N m-1, Bruker) and a scan rate of 5 Hz, capturing 1024 samples per 

line. The standard dual-pass method is adopted in which the first scan tracks the topography in 

amplitude modulation mode and the surface potential profile is determined from the second 

pass with the probe tip lifted over the sample surface at a constant elevation. Throughout the 

characterization, the FET devices were maintained in the grounded status, subjected to gate 



50  Experimental Methods 

 

stress, and subsequently regenerated. All electrical operations on the devices were remotely 

controlled within the measurement cell, under a continuous flow of dry N2 at room temperature. 

For the electrical stress manipulations, the source and drain terminals were grounded and a gate 

voltage of -60 V was applied for durations of 20 s, 40 s and 60 s, respectively. Regeneration 

was achieved by applying a gate voltage of 60 V for 10 min. KPFM measurements were 

initiated immediately following the removal of stress or regeneration gate voltages. The work 

function of the tip was calibrated against a freshly cleaved highly ordered pyrolytic graphite 

(HOPG) before and after the measurements. All KPFM and tapping mode AFM data were 

processed and analyzed with the Gwyddion software. 

 

3.5 X-ray diffraction and spectroscopic techniques 

The molecular alignments of Ph-BTBT-C10 thin films prepared by blade coating and drop 

casting were evaluated through out-of-plane X-ray diffraction (XRD) measurements. These 

measurements were performed under the guidance of Heejung Roh from Prof. Aristide 

Gumyusenge’s lab at MIT, using a Rigaku SmartLab diffractometer with a Cu Kα source 

(wavelength λ = 1.542 Å) in air.  The specular XRD peaks were related to the reciprocal space 

by 
00

4 2
sinz

l

q
d

 


  , where qz is the scattering vector in z-direction, d00l is the interplanar 

spacing of the (00l) planes, and 2θ is the scattering angle. 

 

Grazing-incidence wide-angle X-ray scattering (GIWAXS) measurements were performed by 

Dr Wen Liang Tan from Prof. Chris McNeill’s group at Monash University, using the 

SAXS/WAXS beamline at the Australian Synchrotron with 15.2 keV photons as the X-ray 

source. The 2D scattering patterns were acquired as a function of incident angle by an in-

vacuum Dectris Pilatus 2M detector, where the critical angle that maximizes the scattering 

intensity was around 0.07 - 0.08°.  The incident X-ray beam was precisely focused on a spot 

within the channel region of a large T-shaped FET device, with careful measures taken to 



Experimental Methods                                                                                                           51 

 

  

prevent any discernible beam damage to the OSC film. Prior to the GIWAXS characterization, 

test samples were either left unbiased or subjected to extensive gate sweeps which had resulted 

in a dramatic shift in the threshold voltage. The diffraction patterns of biased and unbiased 

samples were then compared to evaluate whether the electrical measurements induced 

noticeable changes in the molecular packing order. The data reduction and analysis were 

performed using a customized version of the NIKA analysis package implemented in the Igor 

software environment.  

 

In-situ optical absorption spectra were collected using a Perkin Elmer LAMBDA 1050 UV-

Vis-NIR spectrophotometer, in combination with the NEXTRON sub-miniature probe system 

for precise temperature control. Ph-BTBT-C10 thin films were prepared by drop casting onto 

cleaned glass substrates.  

 

Ultraviolet photoelectron spectroscopy (UPS) measurements were carried out utilizing a 

Thermo Fisher Scientific Escalab 250Xi spectrometer (He-I source, photon energy hν = 21.2 

eV), with assistance provided by Dr. Dionisius Hardjo Lukito Tjhe. The measurement 

parameters include a pass energy of 2 eV, a step size of 0.01 eV, and a spot size of 2000 µm. 

An electrical bias of −5 V was applied to the samples to aid in the collection of photoelectrons 

with lowest kinetic energies and facilitate the extrapolation of the secondary electron cutoff 

(i.e. the minimum measured kinetic energy, Ek,min). The work function of gold Au  was 

acquired from the UPS spectrum of a thermally evaporated Au layer on a SiO2/Si substrate, 

employing the relationship  Au k ,max k ,minh E E    , where Ek,max denotes the maximum 

measured kinetic energy of an electron emitted from the Fermi level. To determine the HOMO 

level of Ph-BTBT-C10, the OSC was blade-coated onto the Au layer following the specified 

recipe and exhibited a morphology akin to that observed on SiO2 surfaces. Given that the OSC 

and the gold layer were in electrical contact and their Fermi levels were aligned, the HOMO 

level was deduced accordingly from the width of the total spectrum in conjunction with the 



52  Experimental Methods 

 

known photon energy.  As shown in Fig. 3.5, the work function of Au thin films is 4.9 eV, and 

the HOMO energy of bladed-coated Ph-BTBT-C10 is 5.0 eV. In addition, the difference 

between the Fermi level and the HOMO at the metal-OSC interface, attributed to a shift in the 

vacuum level, is approximately 0.39 eV.  

 

Figure 3.5. UPS spectra for thermally evaporated Au (a) and blade-coated polycrystalline Ph-BTBT-C10 layered 

over Au (b). 

 

 

 

 

 

 

 

 

 

 



 

Chapter 4 Characterizing Charge Transport and 

Trap Dynamics in OFETs across Temperature 

Variations 

 

4.1 Introduction 

With the charge carrier mobility in organic field-effect transistors (OFETs) now steadily 

surpassing that of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), organic 

semiconductors (OSCs) are poised to be superior candidates for future low-cost and flexible 

electronics. The ultimate limits of their electrical performance can be elucidated by exploring 

the nature of charge transport mechanisms. Routine examination of the temperature 

dependence of field-effect mobility of OSCs helps to discern between band-like and thermally 

activated transport regimes across different temperature ranges and material systems. Typically, 

delocalized charge transport with high mobilities is anticipated in pure single crystals and 

highly crystalline thin films of molecular semiconductors (MSCs) at temperatures roughly 

below the room temperature (RT)34,208, whereas the presence of structural defects in 

polycrystalline thin films induces significant localization of charge carriers209,210, often leading 

to a positive temperature coefficient of mobility. It is therefore critical to understand how 

variations in molecular order, packing, and morphology trigger the emergence of distinctive 

energetic disorder in the form of localized electronic states, which hinder the determination of 

intrinsic transport coefficients in molecular semiconductors.  

 



54                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

The spectral density of localized electronic states within the band gap, commonly known as 

the trap density of states (DOS) can be assessed indirectly through experimental techniques 

such as photoemission spectroscopy211, Kelvin probe force spectroscopy212, electron spin 

resonance57, electrical transport measurements, among others. Various analytical methods have 

been developed to derive the trap DOS from the transfer characteristics of field-effect 

transistors213. A well-established methodology, originally devised by Grünewald et al.214 for a-

Si:H TFTs, has been successfully adapted to evaluate the DOS in OFETs. This approach 

applies to the linear regime under the gradual channel approximation, and it assumes 

uniformity of the semiconductor layer perpendicular to the OSC/dielectric interface. In the 

following paragraphs, we will delve into the core components of this formalism and outline the 

essential assumptions made in its application. 

 

The gate-induced total charge carrier density n(x), where the x-axis is defined from the 

OSC/dielectric interface in the perpendicular direction (see Fig. 4.1a), is given by a one-

dimensional Poisson equation: 

                                                             
 2

2
0

( )

s

V x en x

x  





.                                                       (4.1) 

Here, V(x) is the electrostatic potential at position x, ε0 is the permittivity of free space, and εs 

denotes the dielectric constant of the semiconductor, which we assume to be around 3. The 

continuity of the dielectric strength at the OSC/dielectric interface leads to 

 
0 0 0

g fb
s x diel

V VV x

x l
   


  


.                                        (4.2) 

As depicted in Fig. 4.1b, we have considered that the applied gate-source voltage corrected by 

a nonzero flat-band voltage, Vg – Vfb, results in a predominant drop of the electrostatic potential 

across the gate dielectric of thickness l, with a minimal interface potential V0 at the junction 

with the OSC layer of thickness d. Adopting the Boltzmann approximation for the current flow 

in the accumulation channel, we have 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         55 

 

  

 0

0
exp

d

B

eV xI
I dx

d k T

 
  

 
 ,                                              (4.3) 

where I0 is the current at the flat-band condition. Note that the current I is also a function of the 

overdrive gate voltage, Ug = |Vg – Vfb|. Assuming that the electrostatic potential at the surface 

of the OSC is essentially zero under all biasing conditions, i.e. V(d) = 0, and referring to the 

other boundary condition of Eq. 4.2, the following differential equation can be derived: 

 
0

0 0exp 1
gdiel

g s g B

UdV d d

dU l dU eV k T

 
 

   


,                                (4.4) 

in which the current terms have been replaced by the measured field-effect conductivities 

( d dL W I V   ) to normalize the effects of channel geometry and source-drain electric field. 

A partial integration of this equation yields a formulation that implicitly contains V0 as a 

function of Ug: 

   0 0

0 0

exp 1
gU

diel
g g

B B B s

eV eV de
U U u du

k T k T k T l

  
 

  
      

    
 .                 (4.5) 

For each applied gate voltage, the interface potential can be evaluated numerically. The total 

charge carrier density at the semiconductor/dielectric interface (x = 0) is then derived from the 

Poisson equation with the said boundary conditions: 

 
1

2
0 0

0 2
diel

g
s g

V
n V U

l e U

 



 

    
.                                          (4.6) 

Under the zero-temperature approximation, where the Fermi-Dirac distribution is 

approximated as a step function, the density of states N at energy eV0 relative to the Fermi level 

EF is expressed as215  

  0
0

0

( )1 dn V
N eV

e dV
 .                                                      (4.7) 



56                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

It is a common convention to reference the DOS function to the transport level, e.g., to the 

highest occupied molecular orbital (HOMO) or the valence band edge (Ev) in a p-channel 

transistor, provided that the energy difference Ev – EF is known. One way to estimate Ev – EF 

involves assuming that at a specific (or extremum) Ug, the band bending at the OSC/dielectric 

interface aligns the valence band edge with the quasi-Fermi level, so that this energy difference 

can be obtained from the corresponding value of eV0 (Fig 4.1c). This estimation can be 

corroborated through experimental determination, such as the UPS measurement of Ph-BTBT-

C10 discussed in Chapter 3 (refer to Fig. 3.5), which yields a value of around 0.39 eV at room 

temperature.  While there is some inherent uncertainty in this estimation, it does not alter the 

shape of the DOS function but merely results in a systematic shift in the trap depth. Generally, 

the uncertainty does not compromise the validity of our analysis, allowing us to interpret the 

charge transport behaviour in Ph-BTBT-C10 based on the established DOS profile. 

 

 

 

 

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         57 

 

  

 

Figure 4.1. Band bending and potential distribution in a p-channel OFET. a, Schematic representation of the 

semiconductor band bending scenarios: (i) in the absence of an applied gate-source voltage, (ii) with a flat-band 

voltage compensating the initial band bending, and (iii) with a greater gate voltage that induces charge 

accumulation and slight shifts in the conduction and valence band energies. b, Schematic of the potential drop 

across the gate dielectric and the semiconductor layer. The contribution of interface potential is assumed to be 

minimal. c, Illustration of a trap state with an energy E being raised at the dielectric/semiconductor interface to 

coincide with the Fermi energy of the semiconductor. Adapted and reproduced from ref. 216,217. 

 

In this study, we fabricated bottom-gate, top-contact Ph-BTBT-C10 transistors using drop 

casting and blade coating techniques to deposit films with two contrasting levels of crystallinity. 

We explored the different temperature dependencies of field-effect mobility through standard 

two-probe and gated four-probe measurements. In the highly crystalline drop-cast thin film, a 

negative dµ/dT from 80 K to 300 K clearly demonstrates band-like transport, whereas the 

blade-coated polycrystalline device exhibits a more complex µ – T pattern unrelated to contact 

effects, suggesting a transition across different transport regimes. By analysing the distribution 

of electronic states near the band edge in both samples according to the Grünewald approach, 

we propose that intrinsic charge transport in low-disorder OFETs is dominated by delocalized 



58                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

carrier motion intermittently hindered by shallow traps as rationalized by the multiple-trap-

and-release model. Meanwhile, in the polycrystalline OFET which contains extensive 

structural defects yet maintains long-range molecular ordering, charge transport appears to be 

governed by a hybrid mechanism. This mechanism involves bandlike transport in extended 

states and thermally activated transfer among localized states, which dominate alternatively 

across different temperature ranges. Although more experimental evidence would further 

corroborate our findings, we contend that revealing the density of states in organic 

semiconductors significantly aids in interpreting variations in device performance due to 

temperature or carrier concentration changes, and hence shedding light on the subtleties of 

transport physics across various levels of static disorder.  

 

4.2 Investigating the temperature dependence of field-effect 

mobility 

Drop casting of Ph-BTBT-C10 results in a series of thin crystals of varying sizes and thicknesses 

that change in integral multiples. AFM surface height imaging across these crystals unveils a 

step-and-terrace structure, with a typical step height of approximately 5 nm (Fig. 4.2a), 

corresponding to a bilayer of Ph-BTBT-C10 with the molecular long axis (the c-axis) aligning 

roughly orthogonal to the substrate plane. We selected a crystalline region with a generally 

uniform thickness equivalent to two molecular bilayers to serve as the active layer of a bottom-

gate, top-contact field-effect transistor, utilizing a patterned four-probe geometry with 

dimensions summarised in Fig. 4.2. As captured by the cross-polarized optical micrographs in 

Fig. 4.2b, this crystalline film generally consists of a single crystalline domain despite the 

presence of a few voids or aggregates of thicker molecular stacks (yellowish regions), as the 

entire film colour shifts from dark to bright upon rotating the sample by an azimuthal angle of 

around 45°. The room-temperature transfer characteristics at a source-drain voltage Vd = -5 V 

measured in ambient conditions are displayed in Fig. 4.2c. A desirable linear relationship 

between the source-drain current Id and the gate voltage Vg was observed, from which a linear 

extrapolation yields a two-probe mobility µ2p of around 3.5 cm2 V-1 s-1. The transistor exhibits 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         59 

 

  

a reliability factor in excess of 84%, while the deviation is largely attributed to the contribution 

from the threshold voltage of -9 V.  

 

 

Figure 4.2. Drop-cast thin crystals of Ph-BTBT-C10 and a representative bottom-gate, top-contact OFET. a, AFM 

topography along the edge of a very thin crystal, displaying an equivalent thickness to one molecular bilayer (~ 5 

nm) on a SiO2/Si substrate. b, Cross-polarized optical micrographs of a drop-cast thin film covered by Au contacts 

for the source (S), drain (D), and voltage sense probes (VP1 and VP2). The two Au strips atop the thin film are 

idle, disconnected electrodes and do not affect the electrical measurements. c, Linear-regime transfer 

characteristics of the device depicted in b, tested under ambient conditions. The methodology of extracting device 

metrics from the curve is illustrated, and the corresponding channel dimensions are detailed.  

 

To gain further insights into the intrinsic charge transport mechanism in this molecular crystal, 

we examined the temperature dependence of the electrical characteristics over an extended 

range of 80 to 300 K. Figure 4.3a and b show the respective transfer curves as the gate voltage 

sweeps from +10 V to -100 V at each temperature, while Vd is maintained at -5 V or -10 V. We 

observed a continuous positive shift of the threshold voltage Vth (Fig. 4.3c), and a consistent 

decrease of the linear-regime carrier mobility with increasing temperature from 100 K to RT 

(Fig. 4.3d), indicating a band-like transport across this range (dµ/dT < 0). At 80 K, the mobility 



60                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

appears saturated, potentially suggesting a threshold below which a previously reported 

thermally activated regime (dµ/dT > 0)  might occur due to substantial carrier trapping at very 

low temperatures218. The gentle Vg dependence of extracted µ2p is illustrated in Fig. 4.3e and f, 

further substantiating that the observed trend does not stem from significant deviations from 

the ideal Schottky model or artefacts during curve fitting.  

 

 

Figure 4.3. Variable temperature measurement of the crystalline thin-film transistor prepared by drop casting. 

Transfer characteristics at temperature ranging from 80 K to 300 K, with a source-drain voltage of -5 V (a) and -

10 V (b). c, Extrapolated threshold voltage versus test temperature. d, Temperature dependence of the two-probe 

linear regime mobility. Gate voltage dependence of the field-effect mobility extracted from the slope of transfer 

curves at  Vd = -5 V (e) and -10 V (f).  

 

To ascertain whether temperature-dependent contact effects obscure the accurate 

characterization of charge transport behaviour, we determined the channel conductance (Fig. 

4.4a and b) and the contact resistance-immune four-probe mobility µ4p (Fig. 4.4c and d) based 

on gated four-probe measurements. It is important to note that corrections have been made for 

the finite widths of the voltage sense probes, ensuring that the channel dimension parameter 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         61 

 

  

we used are precise. The similar temperature evolution observed in the four-probe channel 

characteristics further supports the presence of band-like transport. However, it is noteworthy 

that µ4p derived from the slope of four-probe conductance curves are generally higher than the 

two-probe counterparts, with this discrepancy diminishing at higher temperatures. This 

observation can be understood through a detailed examination of the contact resistance. 

Extrapolated voltages at the source and drain ends, assuming a linear potential distribution 

across the channel length, are plotted as a function of Vg in Fig. 4.5a and b. The voltage drops 

attributable to the contact resistance at each specific contact are derived from the difference 

between these curves and the source (Vs = 0 V) or drain (Vd = -5 or -10 V) potentials. While 

the voltage drop at the drain contact remains largely stable, a clear reduction in the voltage 

drop at the source contact is noted as the temperature increases, implying improved hole 

injection. We further present the channel width-normalized contact resistance Rc·W as a 

function of the effective gate voltage, Vg – Vth, at different temperature in Fig. 4.5c and d. At 

initial inspection, an increasing Rc·W with rising temperature might seem contradictory to a 

reduced barrier for charge injection; however, when the contact resistance is illustrated as a 

ratio over the FET resistance (Fig. 4.5e and f), a gradual decrease in Rc/Rtot aligns with the trend 

in the discrepancy between µ2p and µ4p relative to temperature. It is also observed that an 

enhanced source-drain field (Vd = -10 versus -5 V) not only results in a lower Rc·W but also 

reduces the contribution of the contact resistance to the overall electrical resistance in the 

device.  

 



62                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

 

Figure 4.4. Temperature-dependent gated four-probe measurements of transfer characteristics in the crystalline 

TFT. a-b, Four-probe channel conductance at Vd = -5 V and -10 V, respectively. c-d, Associated four-probe 

mobility plotted as a function of temperature, with two-probe linear-regime mobilities included for comparison. 

 

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         63 

 

  

 

Figure 4.5. Variations in contact resistance of the crystalline thin-film transistor due to temperature changes. 

Extrapolated electric potentials at the source (solid circles, close to 0 V) and drain (hollow circles, close to the 

minimum voltage) at temperatures of 80 K and 300 K, with Vd set at -5 V (a) and -10 V (b). c-d, Channel width-

normalized contact resistance plotted as a function of the effective gate voltage at various temperatures. e-f, Ratio 

of determined contact resistance to total electrical resistance across different temperatures.  

 

In response to the substantial proportion of contact resistance, we integrated a thin layer of 

molybdenum oxide (~ 5 nm) beneath the gold source/drain contacts to enhance charge injection. 

The characterization of a representative contact-engineered top-contact FET at Vd = -10 V is 

detailed in Fig. 4.6 (with additional measurements and analyses at Vd = -5 V provided in Fig. 

A1.2 in the Appendix). It is clear that the voltage drop at the source/drain electrodes has been 

significantly reduced (Fig. 4.6d), leading to an Rc·W below 1 kΩ·cm (Fig. 4.6e), which 

surpasses previous reports of contact resistances in Ph-BTBT-C10 thin-film transistors219,220. 

Consequently, there is a very close match between the two-probe and four-probe mobilities 

(Fig. 4.6c and Fig. A1.2c), indicating effectively mitigated contact effects. Thus, we concluded 

that the observed decrease in hole mobility with increasing temperature reflects the intrinsic 

charge transport behaviour in (nearly) single-crystalline FETs within the considered 



64                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

temperature range. Attempts to fit the µ4p – T relationship in Fig. 4.6c with a power law (µ ~ 

T-n) yield an exponent n ≈ 0.8, aligning closely with the value reported in C8-DNTT-C8 by 

temperature-dependent photoconductivity measurements94.  

 

Figure 4.6. Variable temperature measurements of a drop-cast crystalline thin-film transistor with a contact 

insertion layer of molybdenum oxide. a, Transfer characteristics with Vd set at -10 V, with detailed channel 

dimensions provided. b, Four-probe channel conductance. c, Extracted two-probe and four-probe mobility plotted 

as a function of temperature. Variations in the threshold voltage are illustrated in the inset. d, Extrapolated 

potentials at the source and drain contacts at temperatures of 80 K and 300 K. e, Gate-dependent contact resistance 

as a function of temperature. f, Ratio of contact resistance over total electrical resistance with increasing 

temperature.  

 

It is indeed audacious to assign a single n value obtained from FET measurements to a specific 

molecular semiconductor as an indicator of its inherent charge transport properties. As we will 

demonstrate subsequently, the temperature dependence of field-effect mobility is critically 

influenced by the thin film morphology and microstructure. We also fabricated staggered 

OFETs using polycrystalline thin films of Ph-BTBT-C10 prepared via blade coating. As seen 

in Fig. 4.7a, the blade-coated film remains highly orientated, as evidenced by the overall 

change in colour contrast when rotated by ~ 45° under a polarized optical microscope. However, 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         65 

 

  

its top surface is comparatively rougher than that of the drop-cast crystalline sample, and the 

bulk film features a variety of domains with differing thickness and crystalline orientations, as 

indicated by the changes in pattern colour and contrast when the sample is rotated. The complex 

surface topography likely arises from the interplay between the shearing force imparted by the 

blade (with its inherent roughness), local concentration gradients and solution flow along the 

meniscus receding line, as well as emerging transient or metastable phases during the solution-

based self-assembly of molecules221. Figure 4.7b shows the RT transfer characteristics in the 

linear regime of a two-probe transistor fabricated from a bladed coated film. In comparison 

with the previously discussed drop-cast sample, this polycrystalline thin-film transistor exhibits 

a similar threshold voltage (~ -10 V) and a reasonably good two-probe mobility of 

approximately 2.9 cm2 V-1 s-1, with a reliability factor of around 82%. However, variable 

temperature measurements of the blade-coated thin-film transistors reveal distinct µ – T 

relationships. Instead of exhibiting a power-law-like temperature dependence of mobility, with 

increasing temperature from 80 K to 300 K, we observed a crossover from a negative dµ/dT to 

a positive slope such that mobilities near RT are significantly higher than those just above 200 

K (Fig. 4.7e). Remarkably, the same trend was observed under varying levels of source-drain 

field in other polycrystalline TFTs (with Vd set to -1 V for Fig. 4.8a-d, and also for the saturation 

regime with Vd = -60 V in Fig. 4.8e-f). Examining the temperature dependent Rc·W (Fig. 4.8d) 

reveals that the rebound in mobility close to RT is not induced by dramatic variations in contact 

resistance or a significant reduction in Rc/Rtot. We could think of several factors that might 

account for the peculiar mobility-temperature dependence. One possibility is the occurrence of 

bias-stress degradation as the temperature approaches RT, giving rise to a large shift of the 

transfer curve towards the negative Vg direction. The bias stress instability has typically been 

ascribed to adsorbed water molecules at the dielectric interface222,223. Their diffusivity is greatly 

suppressed at low temperatures, meaning this type of FET instability is only activated when 

the temperature exceeds a certain threshold. As illustrated in Fig. A1.3a and b, because the µ – 

Vg curve peaks and then gradually declines with further enhancement in Vg at any given 

temperature (as a result of carrier trapping/scattering at the semiconductor-dielectric interface), 

extracting the mobility repeatedly by linear fitting across the same extended gate voltage 

interval could falsely appear to increase the slope due to the negative shift of the transfer curve. 



66                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

This gate bias-stress induced instability in Ph-BTBT-C10 will be explored in Chapter 5. 

However, given the mild electrical testing conditions employed and the long waiting period of 

over 30 minutes between measurements at two consecutive temperatures, we anticipate that 

bias stress degradation is minimal and likely recoverable within the set timescale (refer to Fig. 

A1.3c for the changes in electrical characteristics for two successive gate sweeps to -100 V at 

RT). While the possibility of contact degradation or Fermi level pinning occurring solely in the 

polycrystalline thin film—but not affecting the single-crystalline sample—seems unlikely, 

another plausible explanation could be that, beyond certain threshold temperatures, a thermally 

activated mechanism started to dominate over charge scattering or collisional processes, 

thereby enabling more mobile carriers for electrical conduction. Such scenario is not 

theoretically implausible – for instance in the small polaron transport theory outlined in Chapter 

2 (refer to Fig. 2.1c), a transition from a power-law µ – Vg relationship to Arrhenius-like 

behaviour is explained by the dissociation of polaronic band. It is crucial to note that the 

mobilities typically observed in polycrystalline Ph-BTBT-C10 transistors are too high to be 

treated as pure hopping of charge carriers alone. Thus, charge transport in polycrystalline thin 

films is more likely to be a hybrid process that involves both localized and extended electronic 

states.  

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         67 

 

  

 

Figure 4.7. Variable temperature measurements of blade-coated polycrystalline thin-film transistors. a, Cross-

polarized optical micrographs of a blade-coated polycrystalline thin film. b, Room temperature measurement of 

a two-probe FET characterized under ambient conditions. The inset provides an optical micrograph of the device. 

c-d, Transfer characteristics (c) and four-probe channel conductance (d) of the device shown in a at various 

temperatures. e, Extracted mobility as a function of temperature.  

 



68                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

 

Figure 4.8. Additional variable temperature measurements of blade-coated polycrystalline thin-film transistors. 

a-d, Variations in electrical characteristics of another blade-coated four-probe FET at Vd = -1 V across different 

temperatures. a, Transfer curves with detailed device dimensions; b, Four-probe channel conductance; c, Two-

probe and four-probe mobility; d, Channel width-normalized contact resistance, with the ratio of contact resistance 

to the total device resistance included in the inset. e-f, Characterization of a two-probe FET in the saturation 

regime, with the channel dimensions presented in e.  

 

4.3 Analysing trap density of states using the Grünewald 

approach  

To elucidate how charge carrier transport in Ph-BTBT-C10 FETs is limited by trap states, we 

employed the Grünewald approach to extract the trap DOS and correlate it with temperature-

dependent gate sweeps. We assumed a uniform OSC layer with a thickness of ~ 10 nm and a 

dielectric constant of 3. The channel conductivity measurements were utilized, and the flat-

band condition was treated as the onset of channel conductance (the turn-on voltage), which 

corresponds to a source-drain current of ~ 10-1 nA, as shown in Fig. A1.4a in the Appendix. 

Initially, the interface potential V0 as a function of the overdrive voltage Ug is numerically 

determined, as depicted in Fig. 4.9a. Next, the total charge carrier density n (V0) is derived from 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         69 

 

  

the first order derivative of V0 against Ug (Fig. 4.9c), in accordance with Eq. 4.6. Considering 

the boundary condition that the electrostatic potential at the OSC surface is zero, it is necessary 

that the Debye length in the semiconductor, given by 2
s 0D Bk T e n   , is essentially smaller 

than the thickness of the OSC layer216. With the extremum charge density exceeding 1017 cm-

3, the calculated maximum Debye length is usually below 10 nm, ensuring that the boundary 

assumption remains valid even when the applied gate voltage just slightly surpasses the flat-

band volage Vfb. We filtered the relevant data points and calculated the trap DOS as a function 

of the energy relative to the Fermi level, eV0. As the V0 (Ug) function is numerically solved 

based on Eq. 4.5 by substituting each set of measured FET characteristics, the plot in Fig. 4.9a 

might not be smooth which gives rise to abrupt anomalies in the first derivative and 

consequently in the resultant trap DOS function, especially when the gate-voltage sweep steps 

are narrow and the datapoints are numerous. Hence, we applied typical curve smoothing 

algorithms available in the SciPy scientific computing library, including a B-spline 

representation (with the spline fit set to degree 3 and a specified smoothing condition), and a 

Savitzky-Golay filter (with polynomial fitting of order 3 and a defined number of coefficients). 

As demonstrated in Fig. 4.9d, both algorithms effectively smoothed the trap DOS curves 

without introducing additional artefacts that could mislead our analysis.  

 



70                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

Figure 4.9. Extraction of trap density of states using the Grünewald approach. a, Interface potential solved as a 

function of the overdrive gate voltage. b, First derivative of the curve shown in a. c, Total charge carrier density 

plotted relative to the interface potential. d, Trap DOS as a function of the energy relative to the Fermi level. The 

blue curves highlight the region selected for curve fitting. 

 

However, inspecting the magnitudes of n(V0) and the resultant DOS in Fig 4.9c and d reveals 

values that are strongly exaggerated and unphysical for a typical OFET, where the total charge 

carrier density should be up to ~ 1020 cm-3 224. This issue has been overlooked in several 

implementations of the Grünewald approach for organic small molecule FETs using SiO2 

dielectrics225,226. We believe this systematic artefact stems from a very weak dependence of V0 

on Ug at high gate fields, as indicated by a slope in Fig. 4.9b approaching zero. Referring to Eq. 

4.6, n(V0) is inversely proportional to 0 gV U  and thereby escalates to unphysical levels. 

Taking a step back to numerically solve V0 based on Eq. 4.5, the right side of this equation 

should vary almost quadratically with Ug, assuming the drain current depends linearly on the 

gate voltage, as predicted by the ideal FET model. On the other hand, the left side, represented 

by a sum of exponential and linear functions, rises more dramatically with V0, leading to 

minimal changes in V0 as Ug continues to increase. In our FET measurements, including 4-

probe characteristics, we observe a mobility peak at a moderate Ug, after which d gdI dU  

decreases (Fig. A1.4b). This trend likely causes an even slower increase of the right-hand side 

with Ug, further diminishing changes in V0 and consequently leading to an overestimation of 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         71 

 

  

the charge carrier density. Therefore, we must exercise caution when selecting the appropriate 

range of V0 to yield meaningful DOS values for quantitative analysis. Instead of assuming that 

the quasi-Fermi level crosses the valence band edge at the limit of maximum Ug, we adopt the 

approach suggested by Za’aba et al.227 and practiced by others216, where this energetic 

condition is met when the measured effective charge carrier mobility peaks. Consequently, we 

can identify the particular Upeak and treat the corresponding V0 as EF – EV (Fig. A1.4c). Data 

points with higher interfacial potentials have been omitted to avoid confusion regarding 

unphysical magnitudes of carrier density and trap DOS. In practice, we have excluded the left 

tail portion of the plot in Fig. 4.9d when performing curve fitting. These data points correspond 

to very low values of V0 when the applied gate voltages are still well below the threshold 

voltage. Significant perturbations caused by contact effects or inaccurate sensed potentials 

from the voltage probes during the transition from the off-state to the on-state impede the 

accurate determination of the infallible DOS for deep traps that are far from the band edge. The 

region of interest, with Ug ranging from 5 to 40 V and associated eV0 values from 0.20 to 0.36 

eV, is marked by blue curves in the respective panels of Fig. 4.9. 

 

We first examined the DOS extracted from the room temperature measurement of the drop-

cast crystalline FETs. It is common practice to apply exponential functions (and sometimes 

Gaussian distributions) to model the quasi-continuous density of states that reside in the 

bandgap, distanced from the valence band edge (the HOMO level) of a p-channel transistor228. 

For instance, the analytical function employed to fit Fig. 4.10 can be expressed as: 

   2 2
1 2

2/ /
1 2

peakE EE E E EN E N e N e Ae
     .                                          (4.8) 

In this equation, the characteristic DOS amplitudes and energy constants of the exponential 

distributions are denoted respectively. Additionally, a third Gaussian term characterized by an 

amplitude A, centre position Epeak, and standard deviation σ is included to account for the 

presence of an extra peak when necessary. In the transistor composed of a highly crystalline 

thin film, the extracted DOS from the Grünewald approach appears to be dominated by two 



72                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

exponential contributions with characteristic energies of approximately 13 meV and 35 meV, 

whereas the Gaussian peaks, which are almost an order of magnitude weaker, are centred 

around 37 meV with a narrow width of approximately 7 meV. The fitting parameters are 

summarised in Fig. A1.5a. The exponential state associated with a characteristic energy of 13 

meV is considered shallow relative to the band edge, given the thermal energy available within 

the temperature range of device measurements, while the energetic difference for the deeper 

distribution is at most equivalent to 4 kBT at 100 K. We envision that charge transport in highly 

crystalline Ph-BTBT-C10 transistors can be comprehend using the classic multiple-trap-and-

release formalism. Within the temperature regime of ~ 100 to 300 K, charge carriers 

momentarily immobilized by shallow traps can be released back to the extended states so that 

the overall density of trapped charges remain very low. Consequently, the temperature 

dependence of mobility in this regime is primarily dominated by band-like transport features, 

characterized by a negative dµ/dT. As the temperature decreases further, for instance below 80 

K, charge carriers spend more time localized in trap states rather than participating in 

conduction, leading to a trap-dominated regime with a positive dµ/dT at low temperatures. The 

transition temperature provides insights into the energetic disorder within the organic 

semiconductor, along with external contributions from the device configuration, such as charge 

scattering or trapping at the semiconductor-dielectric interface. 

 

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         73 

 

  

 

Figure 4.10. Analytical fitting of extracted DOS at RT using the Grünewald approach, for the drop-cast crystalline 

FET shown in Fig. 4.3 (a) and the contact-modified crystalline FET depicted in Fig. 4.6 (b). The energy difference 

between the Fermi level and the valence band (VB) edge is assumed to be approximately 0.36 eV. The blue dashed 

lines represent the individual exponential or Gaussian functions as outlined by Eq. 4.8, and the solid black curve 

denotes the combined sum of these components. Fitting parameters for the exponential distributions are 

summarised in panel c. 

 

Moreover, the extracted DOS for blade-coated polycrystalline thin-film transistors are 

illustrated in Fig. 4.11. Fitting the data with Eq. 4.8 yields characteristic energy constants of 

13 meV and 42 meV. The latter distribution suggests that charge trapping states in 

polycrystalline thin films reside at deeper energy levels relative to the band edge compared to 

the single-crystalline counterparts, which is likely due to significant structural inhomogeneities 

within the films. Consequently, we propose that charge transport processes in polycrystalline 

FETs involves a more complex interplay between thermally activated transitions from localized 

to more extended states and diffusive motion in delocalized states. The varying degrees of 

polycrystalline disorder may induce distinct distributions of DOS within the band gap, resulting 

in a range of field-effect mobilities and their temperature dependencies. Field-induced charge 

carriers captured by deep traps can only contribute to current conduction when there is 

sufficient thermal excitation to lift them out of these traps to higher energy levels where 



74                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

tendencies for delocalization are greater. At sufficiently low temperatures, the predominance 

of charge trapping in deep states would lead to a thermally activated hopping regime, exhibiting 

a µ – T dependence similar to that observed in highly ordered films below 80 K. As the 

temperature increases, the contribution of delocalized carriers begins to manifest due to 

growing thermal energy, allowing charge carriers trapped by shallow traps to revert to the 

extended states and engage in band-like motion. If extended-state carriers dominate, we might 

observe a negative dµ/dT, indicative of band-like transport. Conversely, if the thermal 

excitation of charge carriers to (polaronic) band states is still overshadowed by trapping events 

and hopping processes, the mobility could appear temperature-insensitive or display a positive 

dµ/dT. As temperature continues to rise, the conductivity and mobility of band-like carriers 

decrease, while the processes of detrapping and hopping transfer are enhanced. It is thus 

reasonable to propose that, beyond certain threshold temperatures, charge carriers residing in 

deep traps – which have not previously contributed to transport – can be elevated to shallower 

states. Since direct excitation to band states require very high energy (e.g., kBT equalling 42 

meV corresponds to a temperature of around 490 K), a conversion from deeply trapped charges 

to band-state carriers is more likely to occur through a cascade process. This cascade process 

is generally less probable or slower than transfers from shallow states. As thermal activation 

from deep-lying trap states begins to dominate, the temperature dependence of mobility may 

either stabilize or transition to a thermally activated feature near RT, contingent on the 

contribution of newly released band carriers. According to this formalism, we might also 

anticipate that, at sufficiently high temperatures where the residence time of charge carriers in 

any trap states is minimal, the dominance of band-like µ – T relationship would be restored as 

carriers are easily excited to the band states and contribute to transport through simultaneous 

thermal activation and movement. In Chapter 6, we explored the performance of thin-film 

transistors at temperatures above RT and observed a negative dµ/dT from two-probe transfer 

characteristics. This hypothesized framework is proposed to account for the experimental 

observations of a change of sign in dµ/dT in polycrystalline FETs near room temperature. 

Admittedly, additional temperature-dependent characterization focusing on the thin film and 

device stability (refer to Chapter 5) would be useful to eliminate other possible explanations 

and reinforce the idea that the observed trends in µ –T reflect an intrinsic bulk property of the 

polycrystalline small molecule thin film.  



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         75 

 

  

 

Figure 4.11. Analytical fitting of extracted DOS at RT using the Grünewald approach, for the blade-coated 

polycrystalline FET (four-probe) depicted in Fig. 4.7 (a) and the two-probe FET illustrated in Fig. 4.8 (b). Fitting 

parameters for the two exponential functions are summarised in panel c. Additional parameters for the Gaussian 

function are presented in Fig. A1.5b. 

 

4.4 Summary 

In this chapter, we probed charge transport properties in Ph-BTBT-C10 by studying the 

temperature-dependent electrical characteristics of field-effect transistors from 80 K to 300 K. 

The organic small molecules were processed through drop-casting or blade coating into films 

several nanometres thick, with varying morphologies and crystallinities. In the highly 

crystalline bottom-gated staggered FETs, the extracted linear-regime mobility exhibited a 

gradual decay with increasing temperature, a trend further substantiated by gated four-probe 

measurements. Additionally, we noted that the contact resistance extrapolated from channel 

potential sensing diminishes with rising temperature, indicating an improvement in hole 

injection through the source contacts. To further alleviate contact effects, a thin insertion layer 

of molybdenum oxide was introduced under the contact pads, effectively reducing the channel 

width-normalized contact resistance (Rc·W) to below 1 kΩ·cm and enhancing the consistency 



76                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

between the extracted two-probe and four-probe characteristics. Contrary to a simple power-

law variation of mobility with temperature, the mobility of polycrystalline FETs exhibited 

distinctive temperature dependencies, including a transition into thermally activated transport 

as temperatures approached RT. The peculiar behaviour does not appear to be driven by drastic 

changes in contact resistance or likely to be stimulated by severe bias stress instability. It is 

important to note that we have conducted repeated tests across multiple batches of devices. The 

results presented here are both representative and highly reproducible. 

 

To understand the intrinsic charge transport mechanisms and address the energetic disorder 

induced by structural and morphological inhomogeneities in thin films, we employed the 

Grünewald approach to determine the density of states in the gap, distant from the equivalent 

valence band edge (the HOMO level). We carefully reviewed the basic assumptions of this 

approach to confirm its applicability to our measured FET characteristics. In a nutshell, the 

procedure involves numerically solving for the interface electrostatic potential using an 

equation that incorporates channel conductance and overdrive gate voltage. From this, we 

calculated the total charge density and determined the DOS through differentiation. 

Phenomenological fitting with linear combinations of exponentials was applied to analyse the 

density and depth of trap states. Charge transport in highly crystalline thin films is consistent 

with the multiple-trap-and-release model, in which charge carriers predominantly move via 

delocalized states but are occasional trapped by shallow states within the investigated 

temperature range. This mechanism results in the observed negative dµ/dT, as expected. On 

the other hand, in polycrystalline samples featuring a deeper pattern of trap DOS, the interplay 

between diffusive charge motion over extended states and thermal detrapping and transfer 

within a low-lying ensemble of electronic states leads to a mixed picture of band-like and 

hopping-like transport in the experimentally determined µ – T relationship.  

 

This hypothesized framework offers a perspective on the spectral distribution of electronic 

states and the dynamics of charge carriers across various ensembles of states to comprehend 

the temperature dependence of carrier mobility in OFETs. To further explore the role of charge 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         77 

 

  

trapping in relation to temperature or gate voltage modulation, sophisticated ac Hall 

measurements would be instrumental54,229. When determining the trap DOS from electrical 

characterizations, it is imperative to recognize that the choice of method for calculating the trap 

DOS significantly influences the outcomes213. The Grünewald approach avoids the need to 

extract an activation energy from temperature-dependent measurements, which typically 

necessitates equating it with the interfacial band energy difference. Additionally, this method 

avoids abrupt approximations about the spatial extent of charge carrier concentration. However, 

its limitations include a restricted range of physically viable energies and the corresponding 

DOS, particularly evident under scenarios of high applied gate voltages. Overlooking the 

validity of certain assumptions may result in considerable systematic errors in the analysis, 

highlighting that the analytical formulae may not account for all system behaviours. Therefore, 

continuous refinement and expansion of methodological tools are imperative to ensure the 

applicability of the Grünewald approach across a broader range of scenarios. 

 

Furthermore, while the Grünewald approach derives the trap DOS from transfer characteristics 

of thin-film transistors, it is important to acknowledge that other methodologies may offer 

additional or even more reliable insights. Techniques such as impedance spectroscopy, along 

with optical and thermal methods based on photo- and thermally induced transitions among 

electronic states, present valuable alternatives that could complement or enhance our 

understanding. Given our current focus on device measurements and a lack of technical 

expertise in some of these alternative methods, it is essential to consider integrating these 

techniques into future research. Doing so would not only address the limitations of the current 

approach but also broaden the scope and accuracy of our analyses. Although not conclusively 

verified, it is posited that energetic disorder is more pronounced in polycrystalline samples, 

evident from a deeper distribution of trap states within the band gap. These intrinsic charge 

carrier traps play a crucial role in shaping the charge transport mechanisms in organic 

semiconductor thin films and fundamentally affect the performance of electronic devices. 

 



78                           Characterizing Charge Transport and Trap Dynamics in OFETs across Temperature Variations 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

Chapter 5 Charge Trapping and Bias Stress 

Degradation in Ph-BTBT-C10 Thin-Film 

Transistors 

 

Contributions: The grazing incidence wide-angle X-ray scattering (GIWAXS) measurements 

presented in this chapter were performed by Dr. Wen Liang Tan from Prof. Chris McNeill’s 

group at Monash University. Kelvin probe force microscopy (KPFM) measurements were 

conducted and analysed by Dr. Xinkai Qiu. Interpretation of the KPFM results was a 

collaborative effort between Dr. Xinkai Qiu and myself. 

 

5.1 Introduction 

Advancements in material synthesis and device design based on organic semiconductors (OSC) 

have unveiled a number of promising applications across diverse industries such as display 

technology, renewable energy, telecommunications, and healthcare. The inherent weak van der 

Waals interactions within OSCs confer unparallel mechanical flexibility and ease of processing 

under ambient conditions; however, they also render OSCs prone to defect formation and 

charge carrier localization compared to the inorganic counterparts. The ubiquitous presence of 

traps hinders the transport of charge carriers in OSCs and severely deteriorates the performance 

of organic electronic devices, including organic thin-film transistors (OTFTs). Unravelling the 

origins, distribution, and dynamics of these charge carrier traps remains a crucial challenge in 



80                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

comprehending the intrinsic properties of OSCs and surmounting their limitations for broader 

commercial deployment.  

 

Current theoretical framework for understanding charge carrier traps in OSCs stemmed from 

early investigations into charge transport in disordered inorganic solids230. Echoing the band 

theory used to describe the electronic properties of inorganic semiconductors, the energetic 

distribution of electronic states in organic semiconductors, namely the density of states (DOS) 

function, depicts the extended band in parabolic, exponential, or Gaussian forms, contingent 

upon the level of charge carrier localization in crystalline, polycrystalline or amorphous OSCs. 

Their band edges are often not sharply defined, as the extended states tail into the band gap and 

create localized tail states in the presence of disorder228,231. It has been conventional to equate 

the frontier molecular orbitals of organic materials, i.e. the lowest unoccupied molecular orbital 

(LUMO) and the highest occupied molecular orbital (HOMO), with the conduction band 

minimum and valence band maximum, respectively, of inorganic semiconductors232. Structural 

perturbations or imperfections disrupt the crystal symmetry, introducing disorder and localized 

electronic states energetically distributed within the band gap of the material. These localized 

states, or trap states, can immobilize a charge carrier until an external stimulus—such as 

electric field, thermal energy or photons—liberate it back into the band. Depending on their 

energy relative to the band edges at a given temperature T, trap states are categorized as shallow 

if situated in the vicinity of the band edges (within a few kT, where k is the Boltzmann constant), 

allowing for thermal excitation of trapped charges, or deep if they lie further away. The DOS 

function for the in-gap trap states may manifest as discrete energy levels or follow a quasi-

continuous distribution with an exponential or a Gaussian profile. Whilst charge traps in OSCs 

can arise from various sources, static disorder – such as structural inhomogeneities and 

chemical impurities – is identified as one of the primary intrinsic causes202,233–235. 

Environmental factors like moisture, oxygen, and electromagnetic radiation are also crucially 

related to the formation of trap states217,236–238. In this discussion, we will not delve into the 

dynamic disorder induced by large-amplitude molecular vibrations and electron-phonon 

couplings, which alters the transfer integrals and creates localized tail states, even in ostensibly 

perfect organic single crystals.  



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         81 

 

  

A salient detrimental consequence associated with charge immobilization in OTFTs is the bias 

stress degradation, characterized by a temporary shift of the threshold voltage and a change in 

the on-state source-drain current level upon the continuous application of gate voltage. This 

unstable transistor performance over prolonged operational durations not only complicates the 

accurate assessment of electrical metrics but also hampers their proper function in display and 

sensing technologies. Recent experimental investigations have shed light on the microscopic 

origins of charge localization sites within semiconductor materials197,239,240, dielectrics155,206,241, 

and interfaces between device components242–244, which are postulated as important 

contributors to the bias stress instability. Specifically, water has been identified as a main 

culprit in stress degradation, sparking extensive discussions on the potential mechanisms. 

Much attention has been paid to the polarization effects of water on polaronic state 

formation237,245, its involvement in redox reactions223,246,247, and the modification of the 

potential energy profile of OSCs by water molecules or clusters nested within nanovoids of the 

microstructure248,249, among others. For instance, Sharma et al. proposed that the universal 

features of stress instability in SiO2 dielectric-based field-effect transistors (FETs) can be 

explained by the exchange of mobile holes in the accumulation layer with protons in an 

adsorbed water layer on the SiO2 surface via a redox reaction, followed by reversible proton 

migration into the bulk oxide222,250.  Historically, other mechanisms have also been proposed 

to explain the bias stress degradation in OFETs, including the slow formation of bipolarons 

inferred from the depletion rate of mobile holes being proportional to the carrier concentration 

squared251–253, and the ground-state charge transfer from the OSC channel to localized states of 

the dielectric254. Despite the diversity in suggested processes for charge immobilization, the 

temporal evolution of threshold voltage and source-drain current is usually modelled by a 

stretched exponential function, which was initially formulated to account for the dispersive 

diffusion of hydrogen in hydrogenated amorphous silicon transistors255. In OFETs, the model 

posits that the decrease of mobile carrier concentration is regulated by either the diffusive 

motion of charged species or by a dispersive process with an exponential distribution of local 

environments such as the trap state energies or barrier heights243,256,257: 



82                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

      0 1 expth th th

t
V t V V





                 
,                                (5.1a)

 
 

 
 

 
 

1 exp
0 0 0

d th th

d g th g th

I t V V t

I V V V V




                       

                     (5.1b) 

where Id (0) and Vth (0) denote the initial unstressed source-drain current and threshold voltage, 

respectively;  thV  and  thV   represent the threshold voltage and threshold voltage shift 

when equilibrium has been reached at t   ; τ is the characteristic time constant; and β is the 

stretching parameter ( 0 1  ). An implicit assumption frequently made in the fitting of 

stress-induced effects is that the drain current asymptotically approaches zero at infinite time 

as    0th g thV V V    258; however, this simplification should be empirically verified on a 

case-by-case basis.  

 

Despite remarkable progress in exploring the impact of trap states on charge transport and 

addressing nonideal device performance through refined sample preparation and 

environmental protection approaches, the detailed structural origins, electronic properties, and 

dynamic behaviour of charge carrier traps still remain largely elusive. Research has highlighted 

the importance of morphological imperfections – like dislocations, step edges, and grain 

boundaries–in aggravating charge trapping and bias stress degradation. Yet, interpretations 

deriving from indirect trap characterizations often rest on various levels of assumptions and 

approximations. Moreover, the complexity of multi-layer OFET structures intertwines various 

factors affecting charge localization, obliging careful separation of effects, such as contact 

versus channel degradation, for accurate device analysis. In response to these considerations, 

we conducted a systematic study on Ph-BTBT-C10 thin-film transistors to evaluate the extent 

of gate bias-induced device degradation through modifications in thin film crystallinity, contact 

configuration, and interface conditions. Utilizing Kelvin probe force microscopy, we revealed 

the spatial distribution of long-lived trapped charges in stressed films, showcasing their 

dependence on film heterogeneity. Furthermore, we discovered that trapping dynamics near 

the electrode edges vary with molecular orientations, suggesting differences in the energetic 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         83 

 

  

distribution of traps due to dipolar disorder. Interestingly, we observed a pattern of molecular 

rearrangement near the semiconductor/electrode boundary under a prolonged opposing gate-

source electric field, which could not be reversed through the regeneration process. Based on 

these microscopic observations and temporal monitoring, we outline the necessary conditions 

for such molecular reorganization to occur.   

 

5.2 Examining operational stability through device engineering 

The measurement-induced degradation in the transfer characteristics of Ph-BTBT-C10 thin-film 

transistors is evidenced by significant hysteresis between the forward and reverse gate sweeps 

when the voltage sweep rate is slow. As shown in Fig. 5.1a, the shift of threshold voltage and 

associated drop in source-drain current at a given gate voltage evolve continuously over a 

similar timescale to successive measurement. On the other hand, the linear-regime mobility 

derived from FET transconductance remains relatively unaffected despite after the first gate 

sweep (Fig. 5.1b). This result implies that intrinsic trap states are rapidly filled upon initial 

charge accumulation, while subsequent degradation is dominated by a secondary mechanism 

which immobilizes holes without compromising their mobility. We have verified that the 

overall device instability depends solely on the magnitude of the effective source-gate field and 

the duration of gate biasing, since stressing the device with only a source-drain voltage induces 

significantly less degradation than when stressing with a source-gate voltage and grounding 

the source-drain terminals (refer to Fig. A2.1 in the Appendix). Although the quantification of 

bias stress effects in OFETs has been routinely performed in the literature by fitting the 

threshold voltage shift or source-drain current decay using Eq. 5.1, the interpretation of fitting 

parameters can be misleading and problematic for cross-study comparisons. We attempted to 

stress the device for 300 seconds under applied gate voltages of -30, -40, and -50 V 

consecutively, and fitted the temporal evolution of peak source-drain current using either a 

stretched exponential (Fig. A2.2 a, b and c) or a stretched hyperbola (Fig. A2.2 d, e, and f) 

model. The extracted τ values varied by nearly three orders of magnitude, and did not conform 



84                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

to the anticipated Vg dependence in either case. Hence, a simple adaptation of these models 

fails to illuminate the exact causes of charge immobilization and cannot guarantee an accurate 

assessment of stress stability.  

 

 

Figure 5.1. a, Linear regime transfer characteristics of a top-contact Ph-BTBT-C10 polycrystalline thin film 

transistor upon ten repeated gate sweeps. The sweep rate is about 1 V/s. b, Gate voltage-dependent mobility curves 

extracted from transconductance measurements in the forward sweep direction.  c, Electrical characterization of 

bias stress degradation consists of a non-perturbative gate sweep and a 20 second-gate biasing with a constant 

negative voltage, while source and drain contacts are grounded. The device undergoes a positive regenerating gate 

voltage for 200 seconds after ten sweep-stress cycles.   

 

To assess the rapid changes of transfer characteristics during gate sweeps amidst discrepancies 

among device metrics, we formulated a measurement protocol depicted in Fig. 5.1c. The key 

point is to ascertain the electrical parameters while minimizing bias stress during each step of 

transfer characteristics measurement. For the stressing step, correction to the effective stress 

bias is essential to compensate for the presence of a negative threshold voltage, i.e. we define 

Vstress = Vg – Vth, where Vth is updated based on linear extrapolation from the most recent gate 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         85 

 

  

sweep. We carried out a non-perturbative gate sweep (Step 2 in Fig. 5.1c) followed by a 

constant gate bias for 20 seconds (Step 3), repeating several times in a cyclic manner and 

tracing the evolution of electrical characteristics as a function of the number of gate sweeps. 

Eventually, the device was subjected to a positive gate stress for 200 seconds to (partially) 

neutralize the trapped holes and recover the threshold voltage and associated channel currents 

(Step 4). Note that during all gate stress steps, the source/drain terminals were grounded. While 

connecting all electrodes to the ground or leaving the sample unmeasured can still facilitate 

some degree of device recovery, this process occurs over a slower timescale. An exemplar bias-

stress characterization on a polycrystalline, top contact FET with a stress Vg of -30 V (equating 

to Vstress ≈ -20 V) is illustrated in Fig. 5.2a and b. We noted an overall shift of the threshold 

voltage in excess of 3 V towards the negative Vg direction after nine stress cycles, and the 

stress-induced degradation was more pronounced at an early stage and tended to evolve more 

uniformly after the first or second cycle. This diminishing rate of change following early steps 

remains justifiable, even taking into account the slight variation of Vstress between the first and 

the second/third stress step, i.e. from -21 V to -19 V. As the same device, when fully 

regenerated and subjected to stressed trials with Vg = -40 V, demonstrated lower threshold 

voltage shifts during later cycles (when the magnitude of the equivalent stress voltage exceeded 

26 V) compared to the observed shifts in the first and second steps with Vg = -30 V (see Fig. 

A2.3). 

 



86                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

Figure 5.2. Evolution of transfer characteristics and key electrical parameters under repeated bias stress conditions. 

The figure displays the extrapolated threshold voltage, turn-on voltage, and normalized source-drain current at 

maximum gate voltage as a function of the number of gate sweeps. Data is shown for a polycrystalline (panels a 

and b) and single-crystalline (panels c and d) top contact FET.  

 

As static disorder arising from structural inhomogeneities generally impedes charge transport 

in polycrystalline OSC films, we examined the correlation between film crystallinity and OFET 

stress stability by performing the cyclic measurements on staggered devices with single-

crystalline films. (Refer to the polarised optical micrographs and AFM images in Chapter 4.2 

and the subsequent section for visual differences in crystallinity and morphology.) Enhanced 

film crystallinity resulted in less pinholes or cavities within the channel, while the bias stress 

degradation was mildly ameliorated, as demonstrated in Fig. 5.2 c and d.  It is important to note 

that applying the same Vstress to different samples of the same type does not necessarily lead to 

identical ΔVth. Hence, making direct comparisons of single ΔVth under predefined measurement 

conditions may not yield meaningful insights. Instead, we performed the cyclic characterization 

using three different gate stress voltages across various batches of FETs. Each batch comprised 

at least 10 identical devices on separate substrates, all fabricated under uniform processing 

parameters. We defined the cumulative stress voltage as the sum of three threshold-voltage 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         87 

 

  

corrected Vstress values, representing the overall gate biasing condition experienced by each test 

device. The corresponding stress-induced degradation is quantified by the sum of three ΔVth 

values (i.e. the difference in extracted threshold voltage between the 1st and 10th transfer 

sweeps), which is termed the total shift of threshold voltage. Figure 5.3 presents an example 

calculation of the cumulative stress voltage and the total shift of threshold voltage for a test 

polycrystalline transistor.  

 

To illustrate the varying tendencies of stress-induced degradation across devices with different 

architectures and component attributes, a correlation map between the two voltage parameters 

is depicted, for example, as in Fig. 5.3b. Each data point reflects the results from a specific 

batch of top-contact FETs, differentiated with marker shapes: squares for polycrystalline and 

triangles for single-crystalline active layers. The error bars on the x-coordinates reflect the 

variability of initial threshold voltages across devices within each batch, while the y-coordinate 

error bars provide a statistical representation of the degradation across each test batch. The 

legend “Controlled Deposition” indicates that the deposition of top Au electrodes was 

conducted in an advanced evaporation system. In this setup, the sample stage was positioned 

80 mm from the evaporation boat and rotated continuously at 10.0 rpm during deposition. 

Meanwhile, the sample temperature and metal deposition rate were closely monitored to 

enhance precision in the thermal evaporation process. It is reasonable to expect a positive 

correlation in the figure, indicating that higher level of gate voltages would result in larger 

shifts in threshold voltage. Yet, the extensive scattering of data points can obscure this 

relationship when summarising results from a number of device batches. Generally, if data 

points cluster towards the upper-left region of the panel, the corresponding FETs are suggested 

to be more unstable; whereas locations in the lower-right region indicate greater resilience to 

gate bias stress. Based on the comparison in Fig. 5.3b, it can be inferred that reduced 

crystallinity in thin films of top-contact FETs does not appear to be the most decisive factor 

impairing stress stability. 

 



88                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

Figure 5.3. a, Cyclic electrical characterization of a representative polycrystalline thin-film transistor. The device 

underwent ten stress cycles with Vg set successively at -30, -40, and -50 V. Calculations for the cumulative stress 

voltage (representing overall bias stress conditions) and the total shift of threshold voltage (characterising the 

extent of stress degradation) are presented below. b, Stress correlation map for top-contact FETs, distinguishing 

between polycrystalline (squares) and single-crystalline (triangles) thin films. Green markers correspond to FETs 

with electrodes deposited using an advanced metal evaporation system. Error bars along the x-axis represent 

consistent stress conditions for each batch, while those on the y-axis illustrate the variability in stress degradation 

among devices within each batch.  

 

To explore the potential impact of device architecture, we fabricated bottom-contact FETs with 

blade-coated polycrystalline thin films and Cr/Au electrodes prepared by either shadow mask 

evaporation or photolithography. The primary distinction between the two methods lies in the 

configuration of contact edges: shadow mask evaporation produces a gradual SiO2/electrode 

sidewall transition, while photolithography results in a sharply vertical profile. This transition 

region is crucial in modulating the molecular packing, film coverage, crystal growth mode, and 

charge injection area within the bottom-gated coplanar architecture259. Given the inherent 

randomness of solution-based assembly of Ph-BTBT-C10 molecules and the surface property 

contrasts at the contact edges, these factors tend to give rise to disordered molecular packing 

and incomplete film coverage there, presenting challenges in achieving high-performance 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         89 

 

  

bottom-contact devices via blade coating compared to the top-contact counterparts. Figure 5.4 

illustrates examples of bias stress investigation on optimized bottom-contact FETs with 

electrodes prepared by these two approaches. For these two excellent devices, we observed 

comparatively minor stress-induced threshold voltage shifts: applying a Vstress of around -27 V 

(-26 V) leads to an overall ΔVth of -1.5 V (shadow mask) and -1.4 V (photolithography) after 

nine stress cycles. However, there are still counterexamples (See Fig. A2.4) in which for 

instance stressing another bottom-contact device with Vstress = -28 V yields a threshold voltage 

shift of approximately -8.9 V, in sharp contrast to the stable device behaviour shown in Fig. 

5.4 and even exceeding the stress degradation in top-contact devices. This significant variation 

in stress-induced instability suggests that the localization of mobile holes does not depend 

solely on the device architecture being staggered or coplanar.  

 

Figure 5.4. Evolution of transfer characteristics and electrical parameters of an optimised polycrystalline bottom-

contact FET under repeated stress conditions. Panels a and b depict a device with Cr/Au electrodes deposited via 

shadow-mask evaporation, while panels c and d illustrate those prepared using photolithography. e, Stress 

correlation map for top-contact (squares) and bottom-contact FETs with electrodes fabricated via shadow-mask 

evaporation (black circles) or photolithography (green circles). 



90                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

To further understand the contact effects in FET operation and refine device performance, we 

attempted to thermally deposited an insertion layer between the polycrystalline thin film and 

Au contacts in staggered devices. The incorporation of molybdenum oxide or F4-TCNQ 

significantly reduces the magnitude of threshold voltages to values comparable with optimised 

bottom-contact devices, as demonstrated in Fig. 5.5. The improved ideality of transfer 

characteristics can be attributed to the suppression of metal diffusion or thermal damage to the 

crystalline film during contact deposition260–262, and a mitigation of charge trapping sites in 

regions of the bulk OSC close to their interfaces with the top Au electrodes. Interestingly, we 

noted that the performance enhancement achieved with F4-TCNQ contact doping was less 

pronounced than that with MoOx. Such discrepancy may be linked to the incomplete coverage 

of F4-TCNQ molecules on the OSC film. F4-TCNQ was identified to nucleate via Stranski–

Krastanov growth forming isolated islands of varying sizes and shapes, which were not always 

interconnected (Fig. A2.5). As a result, only portions of the OSC film beneath Au contacts 

benefit from the insertion of these small molecule dopants. To assess whether the intrusive 

deposition of Au onto the OSC film introduces extrinsic defects at the contacts which manifest 

as degradation upon bias stress, we carried out gated four-point-probe characterization to 

analyse contact and channel resistance of a top-contact FET under successive gate sweeps. The 

contributions to total resistance from charge injection through contacts into the accumulation 

layer and charge transport across the channel are represented by respective resistance ratios 

shown in Fig. A2.6c. We observed a slight increase in the portion of contact resistance when 

extracted at an effective gate voltage of -30 V, and the growth in Rc/Rtot is more pronounced at 

lower Vg due to the increased curvature of Rc versus Vg (Fig. A2.6b). These observations imply 

that degradation of the metal-semiconductor interface, or any reduction in the charge injection 

area within the context of the current crowding model127,242, manifests slightly over successive 

gate sweeps. Disruptive metal evaporation can perturb the primary molecular packing near the 

electrodes, with effects likely localized around the contact area and predominantly 

characterised by charge injection issues. These problems have been effectivity mitigated with 

MoOx contact treatment. However, if bias stress degradation were solely caused by molecular 

disorder generated during the deposition of top gold electrodes, we would expect bottom-

contact devices to be completely immune to such impact. Contrarily, our observations of bias 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         91 

 

  

stress instability in bottom-contact devices suggest that the causes of threshold voltage shifts 

and current decay are multifaceted. 

 

Figure 5.5. Evolution of transfer characteristics and electrical parameters under repeated stress conditions for 

polycrystalline top-contact FETs with an insertion layer beneath Au electrodes. Panels a and b depict the 

performance of a device with a molybdenum oxide insertion layer, while panels c and d showcase a device 

featuring contact doping with F4-TCNQ. e, Stress correlation map for top-contact FETs featuring a contact 

modification layer (yellow squares). 

 

Throughout the literature, bias-stress instability is often found to be pertinent to the conducting 

channel, specifically the semiconductor-dielectric interface. Modification of SiO2 gate 

dielectrics with silane self-assembled monolayers (SAMs) through silylation is prevalently 

utilized to passivate interfacial traps, such as hydroxyl groups, and to tune the growth and 

molecular packing of organic semiconductors175,263–265. We employed PTS functionalization of 

SiO2 surfaces via solution treatment; however, the resultant rougher surface morphology 

suggests incomplete SAM coverage, which adversely affects the OSC/dielectric interfacial 



92                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

properties. We observed deteriorated bias stress stability and reduced field-effect mobility in 

PTS-treated top-contact FETs, as indicated in Fig. 5.6a, b and d. It is recognized that a more 

uniform PTS SAM might be achieved under sophisticated, inert atmospheric conditions. 

Moreover, the selection of the end group on silylating agents should be considered carefully to 

align with the specific surface chemistry and energy requirements. The intrinsic dipoles 

possessed by SAM molecules may contribute to the surface potential at the OSC/dielectric 

interface, altering FET turn-on conditions and hysteresis effects; for instance, an ordered 

assembly of PTS would render the surface highly electron-withdrawing266. A long alkyl chain 

is preferred for its resistance to water adsorption but complicates the solution deposition of 

molecular semiconductors. Although all FET tests were conducted in nitrogen-filled 

environment where traces of oxygen and water were kept low, completely eliminating adsorbed 

water molecules on dielectric surfaces remains challenging, even with a uniform PTS 

functionalized layer223. Early reports that support a dominant role for water in bias stress 

instability typically indicate that the degradation occurs only when the temperature exceeds 

200 K – the phase transition temperature of supercooled water. In our research, we investigated 

the temperature dependence of stress degradation through cyclic measurements ranging from 

100 K to 300 K. Experimental findings indicate that degradation pathways cannot be entirely 

suppressed at low temperatures, as illustrated in Fig. A2.7. These observations imply that, 

charge carrier trapping, potentially caused by the nano-inclusion of water within film voids or 

chemisorbed/physiosorbed water at the oxide interface, is not solely responsible for the 

degradation phenomenon we witnessed here. The limited impact of water on the operational 

stability of OFETs is not contradictory to existing models that describe the migration of 

positively charged species from the OSC/dielectric interface to the bulk dielectric, provided 

that liquid-phase water is not a necessity for the generation of these charged species. Moreover, 

we found that encapsulation with Cytop, exceeding 700 nm in thickness, does not eliminate the 

bias stress effect (see blue squares in Fig. 5.6d), although we acknowledge that Cytop alone 

may not fully shield ambient moisture from diffusing into the OSC if the device is operated in 

air226.  

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         93 

 

  

Figure 5.6. a-b, Evolution of transfer characteristics and key electrical parameters for a PTS-treated 

polycrystalline top-contact FET. c, Evolution of transfer characteristics under repeated stress conditions for a 

polycrystalline top-contact FET with laminated Au electrodes. d, Stress correlation map for top-contact FETs, 

featuring different modifications: a PTS layer on the dielectric surface (purple), encapsulated by a spin-cast Cytop 

layer (blue), and with laminated electrodes (red). 

 

The salient features of the severity and dynamics of gate bias-induced degradation in different 

Ph-BTBT-C10 transistors cannot be fully understood through electrical measurements alone. In 

order to visualize any preferential hole trapping sites and elucidate the influence of the contacts, 

we conducted Kelvin probe force microscopy on the samples, employing procedures similar to 

the cycled stress experiments discussed above. The principal findings will be detailed in the 

subsequent section. We concluded this section on device engineering by presenting an effort 

to ameliorate undesired deterioration of the OSC due to electrode deposition in the staggered 

architecture. We transferred pre-deposited Au electrodes by laminating a PVA/PMMA/Au 

stack onto a polycrystalline OSC film on SiO2/Si substrates. The sacrificial PVA layer was 

subsequently dissolved with DI water, and the PMMA-coated transistor arrays were thoroughly 

thermal-annealed. The linear-regime transfer characteristics under repeated sweep and stress 



94                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

are displayed in Fig. 5.6c. We obtained an ideal linear relationship between the source-drain 

current and the gate voltage with Vd = -1 V and a near-zero threshold voltage. On the other 

hand, a positive turn-on voltage and slightly increased off-currents at positive Vg imply the 

presence of negative interface charges. These charges likely induce additional hole 

accumulation to maintain charge neutrality, a process potentially influenced by residual water. 

It is evident that preserving a non-destructive metal-semiconductor interface is essential for 

efficient charge injection and transport through the bulk of the OSC.  

 

5.3 Revealing structure-dependent charge trapping through 

KPFM 

The self-assembly of Ph-BTBT-C10 during blade coating, driven by van der Waals interactions 

among the conjugated cores and terminal phenyl and decyl groups, gives rise to a multilayer 

structure with discontinuous topmost islands. Within the film, OSC molecules are organized in 

a herringbone motif, with the long molecular axis (the c-axis) aligning approximately 

perpendicular to the substrate, and the π-π stacking oriented along the b-axis (Fig. 5.7a). 

GIWAXS characterization of the pristine sample (Fig. 5.7b) reveals that the blade-coated OSC 

film favours a bilayer stacking, in which molecules within each layer are unidirectionally 

oriented but arranged antiparallel with respect to the adjacent layer, forming head-to-head 

orientations along the out-of-plane direction (bulk phase, see Fig. 5.8a, left)267,268. This 

arrangement manifests as pronounced out-of-plane reflections corresponding to an interplanar 

distance of ~ 52.1 Å. 2D GIWAXS patterns for the gate-bias stressed sample show roughly 

similar features. Meticulous analysis of the 1D diffraction profiles along the in-plane and out-

of-plane directions showcases comparatively weak 0kl peaks (Fig. 5.7c), a decreased ratio 

between -1kl and 1kl diffraction intensities (Fig. 5.7d), and less pronounced high-order out-of-

plane reflections, such as the (008) peak (Fig. 5.7e). These contrasts may suggest aggravated 

structural disorder upon intensive gate biasing.  

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         95 

 

  

 

Figure 5.7. GIWAXS analysis of blade-coated polycrystalline Ph-BTBT-C10 thin films. a, Visualization of the 

crystal structure of Ph-BTBT-C10. 2D GIWAXS patterns of pristine (b, labelled “x2_04b” and “x2_05”) and gate 

bias-stressed (c, labelled “x2_01” and “x2_02b”) OSC samples. 1D diffraction profiles along the in-plane (d) and 

out-of-plane (e) directions with associated peak indexes.  

 

To gain microscopic insights into the nature of molecular disorder in bladed-coated samples, 

we first applied Kelvin probe force microscopy on as-prepared OSC films. KPFM revealed one 

peculiar origin of packing disorder: a fraction of flipped molecules exhibiting head-to-tail 

stackings, which results in distinctive surface potential features. As depicted in Fig. 5.8c, two 

regions of identical thickness – approximately 10 nm or four monolayers – were identified, 

with the layer number deduced by measuring surface heights from areas of the substrate devoid 

of molecule coverage. These two regions show minor phase differences owing to varying tip-

sample interactions. Moreover, they exhibit significant disparities in surface potential (over 30 

mV), which presumably stem from the different net dipoles within the molecular stack. The 

asymmetry of Ph-BTBT-C10 generates an intrinsic dipole moment along the longitudinal axis 

of the molecule. In even-numbered monolayers with head-to-head orientation, the molecular 

dipoles are essentially nullified every two monolayers (see Fig. 5.8a, left). However, an 



96                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

assembly of unidirectionally oriented molecules with head-to-tail alignment to adjacent 

monolayers can produce a net dipole and a distinct surface potential compared to the nonpolar 

former case (see Fig. 5.8a, middle). These polar assemblies also contrast with the metastable 

thin-film phase revealed by early structural investigations of Ph-BTBT-C10 thin-film growth 

under near-room temperatures, where molecules assemble into single layers with slightly offset 

antiparallel orientations within each layer269,270 (see Fig. 5.8a, right), resulting in nullified net 

dipoles as does the head-to-head oriented bilayer. Observations of varying surface potentials 

in regions with odd-number monolayers support our inference, since the unpaired topmost 

monolayer can adopt either head-to-head, head-to-tail, or a combination of both orientations, 

leading to uncompensated dipoles and variations in surface potential across different segments 

(Fig. 5.8b). We deduced that the higher surface potential observed with our experimental setup 

corresponds to the head-to-tail orientation with the alkyl chains facing upward, as this 

configuration is less thermodynamically favoured and introduces disorder to the film. Notably, 

similar incongruence between topography and surface potential has been reported recently by 

Yan et al.271, in which the authors combined KPFM analysis and DFT calculations to 

demonstrate that vapour deposition of Ph-BTBT-C10 gives rise to a polar assembly emerging 

atop a bilayer with head-to-head orientation at the substrate interface, and further growth of the 

organic film adopts the metastable thin-film phase without diminishing the net dipoles under a 

film thickness of 20 nm.  

 

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         97 

 

  

Figure 5.8. a, Schematics of the bilayer head-to-head (bulk phase), bilayer head-to-tail, and antiparallel 

monolayer (thin-film phase) structures in the assembly of Ph-BTBT-C10 thin films, depicted as simplified two-

monolayer stackings. The bulk and thin-film phases display zero net dipoles due to the cancellation of molecular 

dipoles, whereas the head-to-tail orientated bilayer exhibits a non-zero dipole moment. b, Cross-sectional height, 

phase and surface potential profiles at locations devoid of molecules and across layers of varying thickness. c, 

Complete 2D topography (left), phase (middle), and surface potential (right) mappings of the film.  

 

KPFM measurements capture the dynamic evolution of surface potential, or the local contact 

potential difference (CPD) between the sample and the tip, under various durations of bias 

stress. In this study, we investigated this evolution close to the semiconductor/electrode 

interface in polycrystalline samples with both bottom and top contact configurations. In an 

unstressed bottom contact device whose electrodes were prepared through shadow-mask 

evaporation, a clear dependence of surface potential on film thickness was observed in areas 

distant from the electrode, which is highlighted on the left edge of Fig. 5.9b. Again, the local 

layer number was determined from the associated surface height, assuming a bilayer thickness 

of around 5 nm. The surface potential of the 4-monolayer region away from the electrode edge 

was similar to that of the nearby 6-monolayer region, both exhibiting lower surface potentials 

than the 4-monolayer-thick region next to the electrode edge. In agreement with our argument 



98                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

that molecular orientation influences the magnitude of surface potential, these observations 

imply that the ideal head-to-head bilayer packing of Ph-BTBT-C10 may be disrupted near the 

electrode, possibly due to variations in surface height or energy. We stressed the device by 

applying a gate voltage of -60 V while grounding the source and drain electrodes at intervals 

of 20 seconds, and sequentially removed the gate and probe the changes of surface potential as 

a result of stressing (Fig. 5.9a). The increase in surface potential of the film upon negative gate 

bias indicates the presence of immobilized field-induced charges within the sample, which 

persist beyond typical KPFM measurement timescales. Intriguingly, trapped charges initially 

accumulate faster near the disorder 4 monolayer regions adjacent to the electrode, as evidenced 

by notable changes in the surface potential profile when stressed for 20 seconds compared to 

the pristine sample (Fig. 5.9b). This disordered molecular packing near electrode edges results 

in a non-nullified distribution of molecular dipoles, which significantly broadens the HOMO 

level and induces in-gap trap states responsible for primary hole immobilization observed upon 

the initial gate bias-stress. This heterogeneity in charge trapping gradually diminished, as a 60-

second stress period led to a more uniform surface potential distribution apart from the 

electrode. Given the timescale of stressing and the slow enhancement of surface potentials 

throughout the sample, this later-stage trapping phenomenon is likely dominated by effects at 

the semiconductor-dielectric interface, in contrast to the fast-trapping mechanism relevant to 

disordered molecules near the electrode edge. This bimodal charge trapping dynamics is 

reminiscent of the observations in FET performance under electrical bias, where the shift of 

threshold voltage is more pronounced during the initial 20 seconds of stressing than in later 

cycles.  

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         99 

 

  

Figure 5.9. a, Schematic of KPFM characterization on a bottom-contact FET. b, Evolution of the surface potential 

distribution in a bottom-contact polycrystalline FET with shadow-mask evaporated electrodes, captured when the 

device was not stressed, stressed at Vg = -60 V for 20 s, 40 s and 60 s, and regenerated at Vg = 60 V for 10 min. A 

cross-sectional profile analysis is displayed in panel c.  

 

Eventually, we applied a positive gate voltage of +60 V for 10 minutes to remove the trapped 

charges and regenerate the device. Although the positive gate bias largely restored the original 

unstressed surface potential profile, a peculiar change was noted in the 4-monolayer head-to-

tail oriented region adjacent to the electrode. Here, the surface potential was not regenerated 

but instead altered to resemble that of the surrounding molecules with a head-to-head 

orientation. This local unrestoration can be attributed to a reorganization of the topmost layer 

induced by the external gate electric field, which neutralized the initial net dipole moment of 

head-to-tail stacking into an ordered head-to-head arrangement. The different orientations of 

either the alkyl or the phenyl group facing upwards is discernible in AFM phase imaging as 

shown in Fig. 5.10b, confirming that the local CPD change stems not from residual trapped 

charges, but from an intrinsic alteration in molecular properties. To determine the specific bias 

conditions inducing molecular flipping, KPFM measurements were repeated at the same 

location with negative gate stressing at intervals of 20 s, interspersed with regeneration. 

According to Fig. 5. 10a, surface potential profiles returned to their original state after 20 s and 

40 s of stressing followed by regeneration. In contrast, continued negative gate stressing to a 

total of 60 s led to field-driven molecular rearrangement, resulting in a local surface potential 



100                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

distinct from previous regenerated patterns, as summarized in Fig. 5.10c. As will be detailed 

in the summary section, several criteria must be met for this interesting phenomenon to take 

place.  

 

Figure 5.10. Electric field-driven molecular rearrangement near the electrodes in a bottom-contact polycrystalline 

FET. a, Evolution of surface potential in response to cyclic stress and regeneration. The device was stressed at Vg 

= -60 V for 20 s, 40 s and 60 s, followed immediately by regeneration at a Vg = 60 V for 10 min. b, Comparison 

of the phase of the Ph-BTBT-C10 thin film as prepared (top) and regenerated after stressing at Vg = -60 V for 60 s 

(bottom). c, Three point measurements taken at randomly selected locations across the electrode boundary region, 

where the topmost molecules are oriented head-to-tail. d, Proposed mechanism for molecular reorientation, where 

the estimated 18° tilt angle was derived from the height slope observed in topographic mapping. 

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         101 

 

  

To examine whether the initial trapping of charges is intrinsically affected by molecular 

disorder, we prepared electrodes by photolithography which creates a steep metal step at the 

channel interface. From the local film height and KPFM measurements of the unstressed device, 

the thin film indicated in Fig. 5.11a comprises six monolayers away from the electrode, 

exhibiting a higher surface potential than the even-numbered monolayers adjacent to the 

electrode edge. Based on the relative magnitudes of surface potential with and without 

uncompensated molecular dipoles, we can assign their molecular orientations in these two 

regions as head-to-tail and head-to-head, correspondingly. Given the inherent randomness of 

film morphology resulting from blade coating, it is likely that such thermodynamically unstable 

phases occupy parts of the channel and are captured by KPFM imaging. We traced the 

evolution of surface potential and presented the behaviour in Fig. 5.11a and b. It is notable that 

the elevation in surface potential at the semiconductor-electrode interfacial region is minimal 

compared to that of the bulk film, suggesting that over this transition region, molecules 

arranged in a head-to-head structure are comparatively immune to charge trapping, or that 

trapped charges dissipate more rapidly once the gate bias is removed. This is in sharp contrast 

to the head-to-tail oriented molecules further from the electrode edge, which show more 

significant increases in surface potential. To better illustrate the correlation between molecular 

orientation and trapping dynamics, we performed a detailed analysis of point surface potential 

measurements taken at three equally spaced locations (2 µm) from the Au electrode. These 

measurements were repeated three times over a stress duration of 60 seconds, and the results 

are presented in Fig. 5.12. A common trend across these three locations is an initial fast increase 

in surface potential with stress time, followed by a slower rate of increase emerges during 

prolonged stress periods, e.g. more than 30 seconds. Such findings align with our prior analysis, 

indicating that charge carrier trapping in the polycrystalline thin film is governed by two 

sequentially occurring processes. The latter, more gradual increase in surface potential can be 

attributed to dielectric-related trapping mechanisms, whereas the initial rapid evolution of 

trapped charges is critically affected by the level of molecular disorder, entailing variations in 

the net dipole distribution stemming from the structural organization of molecules at the 

semiconductor-electrode interfaces. As illustrated in Fig. 5.12b, the head-to-head even-

numbered OSC film demonstrates a reduced capacity for charge trapping or dissipates trapped 



102                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

charges faster when adjacent to the electrode compared to areas further away. In contrast, the 

head-to-tail OSC assembly is more prone to charge trapping or retains the charge carriers for 

longer time, associated with deeper trap states in these regions. It is noteworthy to mention that 

early KPFM investigations by Hu et al. proposed that the detrapping of immobilized charge 

carriers upon removing the gate bias is not solely reliant on the thermal release from trap 

states207. Instead, it is largely determined by the injection and transport of minority charge 

carriers, i.e. electrons for a p-type OSC, which subsequently recombine with trapped holes. 

Hence, an alternative explanation for the distinctive features in surface potentials could focus 

on the subtle differences in the recombination kinetics between injected electrons and trapped 

holes in regions with head-to-head or head-to-tail orientations. Regardless of the specific 

mechanisms involved in hole detrapping, we have presented experimental evidence 

demonstrating that the evolution of surface potential near electrodes under gate bias is critically 

dependent on the resultant molecular dipole orientations.  

 

 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         103 

 

  

Figure 5.11. Characterization of charge trapping in bottom-contact devices fabricated using photolithography 

with controlled crystallinity. a-b, Evolution of surface potential distribution in a FET with a polycrystalline thin 

film (b shows a cross-sectional profile), captured when the device was not stressed, stressed at Vg = -60 V for 20 

s, 40 s and 60 s, and regenerated at Vg = 60 V for 10 min. c-d, Corresponding surface potential evolution in a 

bottom-contact, single-crystalline FET fabricated by blade coating. 

 

To further validate the proposed relationship, film crystallinity was varied by modifying the 

blade coating conditions to yield a nearly single-crystalline thin film across the sharply defined 

electrode edges via photolithography. In this case, we did not observe a transition from 

heterogenous to homogenous trapping within the sample as a function of stress time (Fig. 5.11c 

and d). Closely reflecting the film topography, the surface potential revealed a pronounced 

terraced feature, which progressively elevated with prolonged gate bias. Considering that the 

active layer consists of five monolayers with nearly uniform molecular orientation – as 

suggested by local height, phase information, and unstressed KPFM results shown in Fig. 5.11c 



104                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

– the bulk of the film exhibited a uniform pattern of charge immobilization and trap dissipation. 

We anticipate that the resultant net dipole moment from an odd number of monolayers could 

induce deep trap states; consequently, trapped charge carriers lack sufficient thermal energy to 

escape the traps within the timescale of stress withdrawal and KPFM measurements. In general, 

charge trapping induced by the initial bias stress is primarily determined by the electrostatic 

disorder caused by polar assemblies of the asymmetric BTBT derivative. This disorder is often 

templated by the surface mismatch between the towering electrodes and the dielectric surface 

in polycrystalline thin films. Alternatively, it may arise from uncancelled molecular dipoles in 

a unidirectionally oriented monolayer situated atop the bulk phase bilayers in single-crystalline 

samples. This structure-dependent trapping phenomenon could also explain the observed 

inconsistency in bias stress degradation in bottom-contact polycrystalline FETs. Specifically, 

the shift of threshold voltage could be (at least) partially alleviated at an early stage if the 

antiparallel alignment of net dipole moments of individual OSC molecules is maintained near 

the electrode edges. 

 

 

Figure 5.12. Surface potential evolutions measured at three locations with equal distance of 2 microns away from 

the Au electrode edge.  

 

Tracing the evolution of surface potential in a stressed top-contact device reveals a more 

intricate scenario. The direct deposition of approximately 20 nm of gold onto the 

polycrystalline OSC film led to a high density of scattered Au nanoparticles (NPs) or clusters 

in the proximity of the gradually ascending electrode edge (refer to sample topography in Fig. 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         105 

 

  

5.13a). The presence of Au NPs and their diffusion into the OSC film were validated by a 

characterization of Young’s modulus using AFM (see Fig. A2.8), where Ph-BTBT-C10 layers 

of varying thickness and out-of-plane ordering demonstrates similar elasticity. In regions close 

to the electrode slope, elastic properties of the film are markedly altered, showing features akin 

to bulk gold, albeit with slightly reduced Young’s moduli. Gold nanoparticles dispersed over 

the electrode slope and adjacent head-to-head 4 monolayers have shaped the surface potential 

profile, introducing minor dips for an unbiased sample. Upon gate bias exceeding 40 seconds, 

their surface potentials substantially increased, giving rise to a pronounced jagged pattern 

across the 4-layer head-to-head region, and a clear correspondence observed between 

nanoparticle heights and surface potential values on top of the electrode slope. Despite the bulk 

electrode being grounded during the KPFM measurement, it is quite perplexing to observe such 

pronounced charging upon negative gate stress. One plausible explanation might be that these 

Au nanoparticles were somehow disconnected from the bulk such that a uniform electrostatic 

potential had not been established. Alternatively, what was probed under KPFM might not 

represent the bulk electrode but merely a transition area. Ultimately, this prominent surface 

charge build-up appears to be less relevant to the charge trapping tendencies of OSC molecules.  

 

Additionally, a KPFM stress experiment was conducted on a control device featuring a single-

crystalline OSC film with an electrode thickness of around 30 nm. Similar to the polycrystalline 

scenario, a thin gold layer of less than 15 nm cannot effectively screen the underlying residual 

charges, as evidenced by the increase in surface potential in the electrode region adjacent to 

the exposed OSC film (Fig. 5.13c and d). Although scattered small particles were still present 

among the OSC film, they appeared to be absent on top of the electrode slope this time. At 

odds with the polycrystalline case, these nanoparticles exhibited a higher surface potential than 

both the bulk electrode and the OSC film in their pristine state, while the surface potential of 

the odd number-layered OSC film gradually decreased as it approached the Au contact, 

coinciding with an increase in film thickness. The formation of gold clusters through thermal 

evaporation is a commonly observed phenomenon. Research has shown that while neutral 

metal clusters undergo Brownian coagulation and easily grow into macroparticles, positively 



106                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

charged gold clusters may deposit selectively at specific sites such as a kink-like corner272. The 

adsorption, charge transfer, and interdiffusion of Au adatoms, as well as the subsequent surface 

growth of thin films, are significantly influenced by local surface geometries and 

compositions273. Thus, it is reasonable to link the variances in the distribution and height of 

gold nanoparticles on polycrystalline or single-crystalline OSC films to their differing 

crystallinity and surface electrostatic properties.  

 

 

Figure 5.13. Characterization of charge trapping in top-contact devices fabricated using OSC thin films with 

controlled crystallinity. a-b, Evolution of surface potential distribution in a FET with a polycrystalline thin film 

(b shows a cross-sectional profile), captured when the device was not stressed, stressed at Vg = -60 V for 20 s, 40 

s and 60 s, and regenerated at Vg = 60 V for 10 min. c-d, Corresponding surface potential evolution in a single-

crystalline FET. 

 

The charging effects of Au NPs in conjunction with an inorganic semiconductor substrate have 

been extensively reviewed in the literature274–276. For example, the surface potential of Au NPs 

on titanium dioxide was investigated using KPFM mapping274, which revealed substantial 

electron transfer from TiO2 to the nanoparticles across the metal-semiconductor space charge 



Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors                                         107 

 

  

region, resulting in a lower CPD on the latter. Considering that the work function of small-

sized gold particles tends to be lower than that of bulk Au277, and the penetration of metal atoms 

into the crystalline lattice induces extra structural defects and modified the surface electronic 

states of OSC molecules, further analysis would be necessary to elucidate the interplay between 

gold particles and OSC molecules. The key observation here is that regions covered by Au NPs 

can act as preferential sites for positive surface charges upon gate stressing. Notably, such 

increase in surface potential is reversible when the device is regenerated with a positive gate 

bias. In both top-contact scenarios, we did not find a noticeable difference in the (de-)trapping 

dynamics among molecular stacks, irrespective of the presence of net dipoles along the out-of-

plane direction or their proximity to the electrode slope.  

 

Besides the role of Au NPs in augmenting surface potentials near the slopes of contact pads – 

which obscures the impact of molecular disorder on charge trapping kinetics within the 

underlying channel – another plausible consideration involves the transport pathways of charge 

carriers. Immobilized holes must transverse the entire thickness of the OSC and overcome a 

large access resistance to reach the top gold layer for charge dissipation (If we consider hole 

dissipation through recombination with minority charge carriers, the discussion would shift 

towards the challenges in electron injection and transport). Such difficulties may be 

exacerbated in the case of very thin gold layers, which, as seen in Fig. 5.13d, fail to maintain a 

flat surface potential even when grounded after gate biasing.  

 

We anticipate that the diffusion of Au NPs and the associated damage to molecular ordering 

could be effectively suppressed with an insertion layer of molybdenum oxide or F4-TCNQ. 

Such layers might also preemptively fill the deep trap states induced by polar assemblies of 

OSC molecules near the contact regions, thereby relieving some extent of bias stress 

degradation. Bias stress instability due to trapped charges close to the metal/semiconductor 

interfaces has been reported by Kang et al278. The authors suggested that aliphatic alkyl chains 

in the edge-on structured polymer P(NDI2OD-T2) act as barriers to vertical charge transport, 



108                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

thus promoting the formation of localized polaron pairs and deteriorating FET operational 

stability compared to the face-on structure. However, the elevated global surface potential 

observed in our stressed KPFM measurements suggests that factors other than contact issues, 

such as trapping at the OSC/dielectric interface, also significantly contribute to the overall FET 

degradation as a result of repeated sweep-stress duty cycles. 

 

5.4 Summary 

In summary, we conducted electrical characterization and Kelvin probe force microscopy 

measurements on Ph-BTBT-10 thin-film transistors under cyclic stress conditions, exploring 

variations in device architecture, contact conditions, and film crystallinity, among other factors. 

We observed a bimodal time dependence of the threshold voltage shift and associated current 

decay, coupled with the surface potential elevation, suggesting hole immobilization under 

negative gate bias. This indicates that the degradation initially progresses rapidly and becomes 

more uniform in later stress cycles. The predominant mechanism for the comparatively slower 

instability upon extended bias stress is likely due to trapping events at the dielectric interface, 

as evidenced by a global increase in surface potential for stress durations exceeding 40 seconds. 

In contrast, the initial charge localization is strongly associated with molecular disorder, 

particularly with the polar assemblies of asymmetric organic molecules, such as a head-to-tail 

oriented monolayer stacked on thermodynamically favoured bilayers with head-to-head 

packing. These configurations result in uncancelled net electric dipoles, significantly 

broadening the HOMO level and inducing deep trap states that retain trapped charge carriers 

for extended periods. This molecular disorder-driven charge trapping phenomenon helps 

explain some of the variances and inconsistencies observed in FET characterizations. For 

instance, in a bottom-contact configuration, disturbances in head-to-head bilayer orientations 

near electrode edges—due to distinct surface heights or energy contrasts—may lead to the 

accumulation of immobilized holes primarily in this region, likely due to enhanced trapping 

events or difficulties in the dissipation of trapped charges. Such contact-related disorder 

manifests as more severe instability in FET stress experiments compared to scenarios with 



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nonpolar molecular assemblies along the channel and across electrode edges. Moreover, 

improved crystallinity of the thin film does not necessarily equate to more stable device 

performance, as the primary (de-)trapping of charge carriers is governed by the electrostatic 

disorder resulting from dipolar interactions of molecules within the film. 

 

Furthermore, we have documented molecular reorganization induced by a substantial electric 

field orthogonal to the substrate plane. Based on all KPFM observations, we can infer several 

principles governing the occurrence of molecular rearrangement: 1) A net dipole must result 

from non-cancelled individual dipole moments of asymmetric Ph-BTBT-C10 molecules, such 

as even-numbered monolayers with a head-to-tail structure in the topmost layer; 2) A sufficient 

torque must be applied to this top dipole, facilitated by a tilt angle of molecules in the film 

away from the out-of-plane vertical direction – this rearrangement typically occurred at the 

protruded semiconductor/electrode interface; 3) The dipole direction in the topmost layer 

should generally oppose the external electric field. Given the observed positive surface 

potentials in the 4-monolayer, head-to-tail configuration, it may be prudent to consider that the 

partially positive alkyl groups were exposed to the AFM tip and the topmost molecules aligned 

parallel to the layer below; 4) A reduced crystallinity in the film, such as polycrystalline versus 

single crystalline, ensures considerably low energy compensation needed for molecular 

reorganization due to intermolecular interactions, and a not fully nullified gate electric field 

experienced by the topmost molecules. 

 

While the surface potential features of OSC layers with varying dipole alignments can be 

readily explained in bottom-gate coplanar devices, and significant insights have been gained 

on ensuring defect-free molecular assembly at electrode/OSC interfaces, assessing preferential 

trapping sites as a result of primary gate bias becomes more complex in staggered devices. This 

complexity is partly due to the presence of diffused gold nanoparticles or clusters, which 

display a distinct surface potential profile due to charge transfer with the OSC molecules, 

disrupting the ideal molecular ordering beneath the contacts and potentially introducing charge 



110                                      Charge Trapping and Bias Stress Degradation in Ph-BTBT-C10 Thin-Film Transistors 

 

trapping sites in the access regions. Implementing remedies such as the insertion of a metal 

oxide layer, contact doping, or even direct lamination of electrodes could enhance the ideality 

of FET transfer characteristics and help address issues related to operational stability. We 

highlight the critical role of electrostatic potential homogeneity in thin films composed of 

asymmetrically substituted small molecules with intrinsic dipole moments. In such scenarios, 

dipolar electrostatic interactions become significant due to the unbalanced distribution of 

electronic density. The emergence of energetic disorder, characterized by these 

thermodynamically metastable polar assemblies, is crucial in influencing charge transport and 

trapping phenomena during OFET operation. Due to limited expertise in theoretical 

computation, we have been unable to assess the impact of molecular disorder on the electronic 

properties of the film using density functional theory (DFT) calculations or molecular 

dynamics (MD) simulations. Undoubtedly, further investigations are necessary to elucidate 

aspects such as the energetic distribution of trap states associated with disordered molecular 

packing, and to quantify its impact on charge trapping and device instability relative to 

dielectric interfacial effects. These studies are essential to enhance our understanding of charge 

carrier trapping and bias-induced degradation in organic semiconductor devices. 



 

Chapter 6 Thermal Effects and Phase Transitions 

in Organic Thin-Film Transistors: Exploring 

Transport Properties and Structural Dynamics   

 

Contributions: The X-ray diffraction measurements were conducted jointly with Heejung Roh 

from Prof. Aristide Gumyusenge’s group at MIT. The temperature-dependent Kelvin probe 

force microscopy (KPFM) measurements were carried out by Dr. Xinkai Qiu. Analysis and 

interpretation of all measurements were performed independently by myself.  

 

6.1 Introduction 

Recent years have witnessed enormous development in novel π-conjugated molecular 

semiconductors used as the active layer in high-performance organic electronic devices. Fused 

aromatics with thiophene, particularly heteroarenes such as benzothieno[3,2-

b][1]benzothiophene (BTBT) derivatives (Fig. 6.1a), have emerged as exceptional candidates 

for organic field-effect transistors. These materials boast charge carrier mobilities that can 

exceed 10 cm2 V-1 s-1 and demonstrate supreme ambient stability279–281. Additionally, their 

adaptability for side-chain engineering allows for the design of a variety of symmetric and 

asymmetric alkylated molecular structures, which enhance the solution solubility of the BTBT 

derivatives282,283. Extended alkyl side chains promote a lamellar-like structure in which the 

interlayer separation correlates with the length of the repeating units, and a herringbone 

arrangement of the π-conjugated cores which facilitates efficient orbital overlaps between 



112                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

neighbouring molecules, leading to excellent charge transport properties in thin films284. 

Moreover, the conformational flexibility of the long alkyl chains at elevated temperatures (e.g., 

above 140 ℃) allows these rod-like BTBT derivatives to transition into calamitic liquid 

crystalline mesophases (refer to Fig. 6.1), in which an intermediate level of ordering and 

density is maintained between the crystalline state and isotropic melts. In contrast to the low-

ordered smectic A (orthogonal) or C (tilted) phases, where positional correlation within each 

separate layer (perpendicular to the long-axis of these constituent molecules, or mesogens) is 

very weak, the smectic E (SmE) phase maintains the herringbone packing of mesogenic cores. 

In this mesophase, rotations of mesogens around their long-axis are restricted, preserving the 

π-π interactions285–287 (Fig. 6.1c). This SmE phase appears in 2-decyl-7-phenyl-

benzothienobenzothiophene (Ph-BTBT-C10) during a heating process when the temperature 

surpasses ~143 ℃, and it has been exploited as a precursor for morphological control over film 

uniformity and flatness. The strategic approach yields crystalline thin-film transistors with 

superior charge mobility and high thermal stability288. 

 

In view of the emergence of thermotropic liquid crystalline phases, structural evolutions of Ph-

BTBT-C10 bulk films under thermal treatment and across the phase transitions have garnered 

extensive research interest during recent years. A specific type of molecular disorder, 

characterized by flipped molecules within the head-to-head stacking in the crystalline phase, 

was identified through a peculiar broadening of X-ray diffraction peaks of thin films268, which 

are highly contingent on the crystallization kinetics from elevated temperatures. Spectroscopic 

techniques have been widely employed to characterize the reorganization of molecular 

constituents. For instance, Shioya et al. utilized temperature-dependent in-situ infrared 

spectroscopy to demonstrate that the crystalline-smectic phase transition is trigger by the 

melting of decyl chains, and noted that heat-induced conformational disorder could persist even 

after cooling down289. Additionally, polarized low-frequency Raman spectroscopy has 

revealed that, as the bulk crystal approaches the phase transition temperature, interpenetration 

of crystal bilayers is facilitated by the softening of a displacive phonon mode290. This is 

followed by a discontinuous intralayer rearrangement of the molecular rigid cores into the 

herringbone motif of the SmE monolayer structure. This proposed mechanism of collective 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   113 

 

  

interlayer translations and in-plane rearrangement of conjugated cores was later confirmed in 

single crystal specimens via infrared and Raman spectroscopy291. Moreover, the crystallinity 

of the specimen upon backward transformation is sensitive to the way of thermal treatment, as 

the molecular rotations around their long axis in the smectic mesophase result in crystal 

domains with varying in-plane orientations in the restored sample. 

 

Another intriguing aspect of Ph-BTBT-C10, which has spurred a number of structural 

investigations, is its tendency to undergo a structural transformation from monolayer to bilayer 

stacking through a simple thermal annealing process. Remarkably, this transformation can also 

occur as a result of aging at room temperature, during which the conformation of decyl chains 

evolves into a more ordered state and their melting or self-aggregation plays a significant role 

in this crystalline transition292. As mentioned in Chapter 5, these two configurations are 

commonly referred to as the thin-film phase and the bulk phase. It is noteworthy that while the 

monolayer packings in the thin-film crystalline phase and the SmE phase share a similar head-

to-tail orientation, their exact molecular arrangements within a layer are distinct. The thin-film 

phase exhibits an antiparallel fashion in which the phenyl group and the decyl chain of a 

neighbouring molecule are almost closely aligned (Fig. 6.1d, middle), whereas the SmE layer 

features a nano-segregation of aromatics units from interdigitated alkyl side chains269,293,294 

(Fig. 6.1d, right). The thin-film phase is a metastable phase that usually arises from rapid 

solidification processes and weak nondirected interactions, characteristic of film preparation 

techniques far from thermodynamic equilibrium, such as spin coating with fast solvent 

evaporation and physical vapour deposition270. In this context, multiple co-existing polymorphs 

can form during the nucleation and crystallization from solution at temperatures well below 

the crystal-liquid crystal phase transition221.  

 



114                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

Figure 6.1. Structural analysis and thermal behaviour of BTBT derivatives. a, Molecular structures of common 

BTBT derivatives. b, Differential scanning calorimetry curves for Ph-BTBT-C10, demonstrating thermal phase 

transitions. c, Illustration of molecular arrangements in different phases of matter. d, Schematics of molecular 

packing models: bilayer crystal (left), antiparallel monolayer crystal (middle), and nano-segregated monolayer 

structure (right). Reproduced from ref. 288,295–297.  

 

Despite the well-documented patterns of structural reorganization during phase transitions and 

the identification of molecular disorder caused by reversed molecules, the impact of heat 

treatment and phase transitions on charge transport remains elusive. The dynamics of how these 

structural changes impact charge mobility and overall device performance are not yet fully 

understood. In this Chapter, we explore the transport properties in Ph-BTBT-C10 as the 

temperature rises to approaching the phase transition. Field-effect mobility measurements 

showcase three distinct transport regimes in response to increasing temperature: a slow and 

reversible decay (Regime Ⅰ); a sharp decline attributed to strong device instability, which can 

be recovered over a prolonged period (regime Ⅱ); and a tailing off to zero current, coupled with 

evident morphological destruction (regime Ⅲ). We investigated the presumed structural 

transformations induced by the temperature ramp using in-situ UV-Vis absorption 

spectroscopy and specular X-ray diffraction. These techniques provide valuable insights into 

the evolution of intermolecular exciton couplings, and any perturbations or improvements in 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   115 

 

  

the out-of-plane molecular orientation caused by thermal treatment. Moreover, Kelvin probe 

force microscopy reveals intriguing patterns of morphological deformation arising from 

molecular diffusion, starting from regime II. These findings lead to a coherent interpretation of 

the temperature-dependent electrical characteristics and their recovery dynamics. In general, 

understanding the ordering in molecular organization is particularly crucial for organic 

materials that exhibit liquid crystal mesophases. Modulating the interplay between intralayer 

flip–flop motion and core–core interactions, particularly as the material approaches liquid 

crystalline phases, can effectively optimize film crystallinity and uniformity298. This approach 

is key to overcoming challenges and pursing high performance in organic semiconductor 

devices.  

 

6.2 Evaluating FET performance at elevated temperatures 

We initially assessed the change in FET performance in response to substrate heating, which 

was facilitated by a Peltier element in the microprobe chamber. The transfer characteristics of 

a top-contact Ph-BTBT-C10 transistor, featuring a blade-coated polycrystalline thin film and 

exhibiting moderate performance, are displayed in Fig. 6.2a. We observed a continuous decline 

in the extracted saturation mobility µsat with increasing temperature T. While the transfer 

characteristics shown below detail the performance evolution for the saturation regime, we 

have confirmed that the linear-regime mobility follows a similar trend, as summarised in Fig. 

6.3a, albeit with slight offsets in magnitude at each set temperature. Recalling the temperature-

dependent FET measurements conducted under high vacuum from 80 K to 300 K, as discussed 

in Chapter 4, this decreasing trend mirrors the findings on linear-regime mobility observed in 

highly-crystalline drop-cast samples. On the other hand, the significant regain of mobility near 

room temperature noted in blade-coated films does not extend across a wide temperature range 

to elevated temperatures. We opted not to combine the µ – T data across the entire temperature 

range due to differences in chamber pressure between the two testing environments. 



116                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

Interestingly, the decreasing µsat – T relationship can be categorised into several regimes (Fig. 

6.2b). In Regime Ⅰ, where T ranges from room temperature (~24 ℃) to approximately 85 ~ 

90 ℃, µsat gradually decreases from 2.7 cm2 V-1 s-1 to 2.3 cm2 V-1 s-1. However, as the substrate 

heating surpasses a certain threshold, µsat starts to drop drastically as the temperature increases 

further in Regime Ⅱ, until at sufficiently high temperatures the drain currents become 

comparable to gate leakage, rendering any linear extraction of transconductance meaningless. 

In Regime Ⅲ, where temperatures are above, for example, 120 ℃, we tested a few samples 

that remained sufficiently conductive. Unfortunately, drastic morphological changes were 

readily observable even from the features of discontinuous crystallite islands and thermal 

cracks under optical microscopy (see Fig. A3.1c in the appendix) when pushing the sample 

towards the crystalline/SmE transition boundary. The morphological destruction and the 

associated plummet in carrier mobility are unrecoverable after cooling the sample from this 

high-temperature regime back down to room temperature (RT).  

 

Figure 6.2. Temperature-dependent saturation-regime transfer characteristics of a top-contact, Ph-BTBT-C10 

transistor with a blade-coated polycrystalline (a) and a drop-cast single-crystalline (c) thin film. Extracted charge 

mobilities are presented in panels b and d, respectively. Three transport regimes, each with distinctive curvatures 

in the mobility-temperature relationship, are identified.  

 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   117 

 

  

We conducted gate sweeps with a similar temperature scan on a top-contact FET made from a 

drop-cast single-crystalline thin film. The heating and cooling rates were meticulously 

controlled at 1℃/min to avoid abrupt temperature changes, which can induce severe thermal 

cracks that are commonly seen in single crystals when subjected to hotplate annealing above 

60 ℃ or during the invasive deposition of top electrodes. The three distinctive regimes are 

clearly evident in Fig. 6.2d. A notable feature in regime Ⅲ is a convex bending of the µ – T 

curve observed after 110 ℃. Upon closer examination, this is found to result from an evolving 

suppression of FET conductance at high gate voltages with increasing temperature (Fig. 6.2c). 

This observation is often attributed to charge scattering or trapping as the conductive channel 

becomes more confined to the OSC/dielectric interface, which exhibits more energetic disorder 

than the bulk OSC. It is in fact not a unique characteristic for single-crystalline devices; similar 

patterns have been noticed in polycrystalline samples (see Fig 6.3a), where the nonideal 

behaviour worsens with increasing temperature and also precedes subsequent morphological 

transformations.  

 

To eliminate potential disturbances from oxygen or moisture during heat treatment, we carried 

out a comparative study where samples were pre-stored in a nitrogen-filled glovebox with 

desiccants (98% CaSO4, 2% CoCl2) at least overnight and sealed within the microprobe 

chamber. This arrangement ensured that any inclusion of water molecules within the nanovoids 

or dislocations of the (poly)crystalline film was excluded, and the samples were constantly 

exposed to an inert environment. As depicted in Fig.6.3b, the aforementioned temperature 

dependence of carrier mobility was not replaced, suggesting that oxidation or water-related 

electrochemical reactions are presumably not the fundamental causes. A key difference noted 

is that, the demarcation between Regime Ⅰ and Ⅱ, as well as between Regime Ⅱ and Ⅲ, have 

shifted to lower temperature ranges, occurring at approximately 70℃ for the former transition 

and 90℃ for the latter. Given that air and nitrogen have very close thermal conductivities at 

atmospheric pressure — 26.4 and 26.0 mW m-1 K-1, respectively, at 300 K — the slight over-

pressurization of nitrogen within the sealed microprobe chamber (a few millibars referenced to 

the atmospheric pressure) is unlikely to result in a noticeable difference in the capability of 



118                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

heat transmission between the two testing environments. The observed change in transition 

temperatures may instead arise from a better seal of the chamber, which diminishes heat 

exchange between the heated stage or the internal gas and the external atmosphere, thereby 

stabilizing the samples at the set temperature more effectively. It is important to notice that 

variations in carrier mobility are not influenced by the duration of thermal annealing at a 

moderate temperature in Regime Ⅰ, such as 60 ℃ (refer to Fig. 6.3c). While there might be 

some discrepancies between the actual temperature of the heated sample and the nominal 

temperature set on the Peltier heater, it is clear that the mobility is dependent on the temperature 

itself, rather than the input thermal energy. 

 

Figure 6.3. Temperature-dependent saturation-regime transfer characteristics of a top-contact, Ph-BTBT-C10 

transistor with a blade-coated polycrystalline (a) and a drop-cast single-crystalline (c) thin film. Extracted charge 

mobilities are displayed in panel b and d, respectively. Three transport regimes with distinctive curvatures of the 

mobility-temperature relationship are identified. 

 

Ph-BTBT-C10 has been reported by Iino et al. as a thermally stable compound compared to the 

symmetric C10-BTBT-C10. In their study, thin-film transistors processed by spin-coating 

possess almost unchanged mobilities when remeasured under ambient conditions after being 

subjected to thermal stress at temperatures nearing 140℃ for 5 minutes219. The authors 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   119 

 

  

attributed this impressive thermal durability to the highly ordered SmE mesophase, which helps 

to reduce the likelihood of film melting into droplets at elevated temperatures299. At first glance, 

their observations may seem inconsistent with the strong temperature dependence noted in our 

measurements, particularly the rapid drop in µ during Regime Ⅱ. Indeed, we found out that this 

remarkable decay is related to highly unstable device behaviour. While repeated measurements 

at a given temperature in Regime Ⅰ yield nearly identical transfer characteristics, in Regime Ⅱ, 

the transfer curve shifts substantially towards the negative Vg direction after each sweep, even 

though the device was maintained at thermal equilibrium (see Fig. 6.3d). Although this 

behaviour resembles the bias stress instability discussed in Chapter 5, the magnitude of 

degradation is considerably greater at elevated temperatures within Regime Ⅱ. We have shown 

that, successive gate sweeps at RT induce a continuous shift in the threshold voltage and result 

in a corresponding drop in drain current, without compromising the field-effect mobility (refer 

to Fig. 5.1 for a reminder). For extended durations of gate bias stress, this degradation is 

predominantly determined by dielectric-related immobilization of charge carriers. Therefore, 

the decrease in mobility observed under repeated measurements in Regime Ⅱ cannot be solely 

ascribed to an enhanced bias stress instability, suggesting the presence of additional device 

degradation pathways.  

 

Interestingly, we observed different recovery dynamics pertinent to the specific temperature 

regime. Cooling down the device from a temperature just before reaching the curve shoulder 

of regime Ⅱ (around 70 ℃ in an inert environment) can immediately lead to a regain of mobility 

(Fig. 6.4a), despite some hysteresis among cycled measurements (refer to Fig. A3.1e for the 

corresponding transfer curves). It is quite surprising to notice that, recovery from the 

significantly degraded mobility within regime Ⅱ can still occur over a particularly long 

timescale (typically a couple of days), and exposure to air appears to expedite this process. As 

shown in Fig. 6.4b, once the heated sample was cooled down to RT, the drain current and 

carrier mobility did not immediately revert to their initial values. The sample remained sealed 

in the microprobe chamber and stored in a nitrogen-filled glovebox for four days, yet the 

measured performance afterwards was still low. Subsequently, the sample was taken out and 



120                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

exposed to ambient conditions for another week, and remarkably, the FET transfer 

characteristics were restored (and even slightly surpassed) compared to the pristine status.  

 

A recent study by Huang et al. proposed that oxygen significantly pre-empts donor-like traps 

in organic semiconductors, causing the Fermi level to move closer to the HOMO edge and 

facilitating hole injection through a contact doping effect300. It has also been proposed that with 

extended exposure to air, trapping of the minority charge carriers intensifies and negatively 

impacts FET performance301. Throughout our investigations on Ph-BTBT-C10 thin-film 

transistors, we have not observed any degradation due to ambient exposure lasting up to several 

months or around a year. In this context, the gradual recovery of device performance may be 

related to a beneficial effect of oxygen doping. Additionally, an infrared spectroscopy study by 

Oka et al. revealed that the thin-film phase, characterized by head-to-tail orientated monolayers, 

can transition to the bulk bilayer phase with head-to-head packing through a structural aging 

process under RT292, similar to the effect of thermal annealing a spin-cast film at 120 ℃ 288. 

This process may also contribute to the observed recovery phenomenon. Indeed, we have 

noticed an enhancement in device performance after a period of storage, regardless of whether 

the samples are stored in air or an inert atmosphere (refer to Fig. A3.2). The recovery of thin-

film structure and device performance is a complex topic that warrants further investigation. 

 

 

Figure 6.4. Recovery of charge carrier mobilities in Regime Ⅰ (a) and Regime Ⅱ (b).  

 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   121 

 

  

6.3 Analysing structural transformations upon thermal 

treatment 

We conducted in-situ UV-Vis absorption spectroscopy of Ph-BTBT-C10 thin films as a function 

of temperature using the microprobe chamber. The thin films were prepared by drop casting 

on glass substrates, and the absorption spectrum of an empty substrate was initially acquired 

as a reference for background signals. As illustrated in Fig. 6.5a, the vibronically resolved 

bands at 380 nm (0-0) and 363 nm (0-1) are indicative of π-π* transitions of the conjugated 

cores. The optical bandgap, estimated from the Tauc plot shown in the inset of Fig. 6.5a, is 

calculated to be 3.16 eV for the pristine sample at room temperature, consistent with previous 

photophysical characterization of this compound302.  Gaussian peak fittings were applied to the 

absorption spectra to obtain the peak positions, widths, and intensity ratios of vibronic bands, 

with an exemplar displayed in Fig. A3.3. The more intense (0-0) transition at RT is consistent 

with the behaviour of J-aggregates, which is particularly relevant to the bilayer-type 

herringbone stacking in Ph-BTBT-C10 crystals. Given that the non-polarized incident light is 

normal to the substrate plane, the spectral changes in response to heating can likely be 

explained by variations in the orthogonal molecular orientation from the initial state. Upon 

heating, we observed a noticeable hypochromic shift of the (0-0) band and a significant 

broadening of the (0-1) band at elevated temperatures (Fig. 6.5b). The increased absorption 

intensity of the (0-1) band resulted in a gradual decay in the peak height ratio between the (0-

0) and (0-1) transitions, A0-0/A0-1, from 1.5 to around 0.7 as the temperature rose from 23 ℃ to 

130 ℃. Simultaneously, the sharp apex-like feature at 379 nm became less pronounced and 

eventually, the absorption peaks merged into a broad and featureless band as the phase 

transition to SmE was reached at temperatures exceeding 140 ℃.  

 

A rapid quench from the liquid crystalline phase to lower temperatures immediately restored 

the spectral characteristics (Fig A3.4), and thus the apex feature peaking at ~ 379 nm is a salient 

signature of the crystalline phase. As temperature increases and exciton bandwidth is 



122                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

suppressed, molecules are transformed into a more H-type cofacial aggregates, which can be 

visualized as a gradual interpenetration of bilayers along the c-axis290 (In a revised version, 

Yoneya described this step as a molecular displacement by half the molecular length along the 

vertical long axis c between two adjacent molecular columns293). When the temperature 

approaches the phase transition, there is a sudden in-plane rearrangement of the rigid cores into 

the nano-segregated monolayer herringbone structure. In essence, insights into the structural 

changes within the thin film at elevated temperatures can be gleaned by examining the 

variations in spectral signatures. 

 

Figure 6.5. a, Temperature-dependent UV-Vis absorption spectra of a drop-cast Ph-BTBT-C10 thin film on glass 

The arrow indicates the direction of spectra changes as temperature rises. The inset shows the Tauc plot used to 

estimate the optical gap of this small molecule at room temperature. b, Extracted peak positions, peak widths (full 

width at half maximum), and the peak height ratio between the (0-0) and (0-1) transitions derived from Gaussian 

fitting of the absorption spectra.  

 

We also investigated the heat-induced changes in the out-of-plane molecular packing of Ph-

BTBT-C10 thin films through X-ray diffraction (XRD) measurements. Both blade-coated and 

drop-cast thin films on SiO2/Si substrates were studied before and after a thermal stress. The 

stress involves annealing a sample inside the nitrogen-filled microprobe chamber at 100℃ for 

more than 30 minutes, followed by a slow cooling to RT, mimicking the thermal conditions 

associated with device measurement within Regime Ⅱ. While the blade-coated film was 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   123 

 

  

prepared using the exact parameters for transistor fabrication, the drop-cast sample contained 

millimetre-scale crystalline platelets that were comparatively thicker than the typical two- or 

three-bilayer-thick crystals for OFET channels (see the insets in Fig. 6.6a and c).  

 

The XRD patterns in Fig. 6.6 reveal well-resolved Bragg peaks that can be indexed based on 

the bilayer stacks of the bulk crystalline phase. The peak situated at the diffraction angle 2θ = 

1.7° (corresponding to the scattering vector qz = 0.12 Å-1) is identified as the 001 peak with a 

d-spacing of 5.2 nm, and higher order 00l reflections are nearly equally spaced. For the blade-

coated film (Fig. 6.6a), we observed a reduced intensity and a slight shift of the 002 and 003 

peaks towards larger diffraction angles following the thermal treatment, while the intensities 

of further higher-order peaks increased. On the other hand, for the drop-cast thick crystals (Fig. 

6.6c), the considerably sharper line shapes and stronger peak intensities suggest an increase in 

crystallite sizes compared to the polycrystalline thin film. The Bragg peak intensities remained 

roughly unaffected after annealing, indicating a more resilient out-of-plane structure against 

thermal treatment. 

 



124                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

 

Figure 6.6. Specular X-ray diffraction patterns of Ph-BTBT-C10 thin films, prepared by blade coating (a) and 

drop casting (c), before and after thermal treatment. The insets show optical micrographs of the respective samples. 

Diffraction peak widths plotted as a function of peak positions for the blade-coated (b) and drop-cast (d) samples.  

 

To further analyse the effects of thermal treatment, we fitted the respective diffraction peaks 

with pseudo-Voigt functions to determine the exact peak positions and widths – an illustrative 

example is presented in Fig. A3.5. The results are visualized by plotting the full width at half 

maximum (FWHM) Δq as a function of the peak position qz. As the higher order reflections 

are very weak for the blade-coated polycrystalline sample, only up to the fifth diffraction peaks 

are included in Fig. 6.6b. The subtle positive shift in qz after thermal annealing can be linked 

to a slight lattice contraction in the vertical direction. Meanwhile, the selective broadening of 

lower order peaks and an enhancement of a few higher order reflections may suggest a 

reorganization of molecules, which exerts a dual influence on the packing order. In contrast, 

for the single-crystalline sample subjected to thermal stress, we observed negligible shifts in 

peak positions and a consistent narrowing of peak widths as illustrated in Fig. 6.6d (except for 

the 006 peak where the seemingly broadening is caused by uncertainties in curve fitting due to 

its weak intensity). The narrowing of peak widths is usually linked with an increase in 

crystallite size, as described by the Scherrer equation, Lc = 2 π K/Δq, where Lc denotes the 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   125 

 

  

coherence length, and K is the shape factor. However, the initial negative slope and subsequent 

rebound trend suggest that the classic Williamson-Hall analysis for examining the peak 

broadening contributions from microstrain and crystallite size is inappropriate for our 

observations303. For the blade-coated sample, the general increase in peak width with 

diffraction order suggests the presence of a paracrystalline disorder component; while for the 

drop-cast sample, the complex curvature of Fig. 6.6d may indicate a competition between 

cumulative disorder and crystallite size-related broadening. In general, a more sophisticated 

formalism such as the modified Warren–Averbach method is preferred for determining the 

interplay between thermal fluctuations, variations in lattice parameters, and paracrystalline 

disorder304,305.  

 

Eventually, we examined the morphological variations of the polycrystalline thin film with 

increasing temperature, using in-situ Kevin probe force microscopy (KPFM) to provide a 

unified explanation for the observed changes in FET performance. The KPFM measurements 

were performed in an inert atmosphere, maintained by a continuous flow of dry nitrogen. 

Figure 6.7 illustrates the topography and surface potential (SP) distributions of a blade-coated 

thin film at RT (27℃). We identified regions of five, six, and seven monolayers by measuring 

the corresponding film heights from the exposed bottom surface (Fig. 6.7a – c). The film 

generally exhibits a uniform surface potential across the five- and seven-monolayer regions, 

implying that the majority of the scanned area demonstrates a consistent dipole moment (or 

molecular orientation) in the out-of-plane direction. The slightly lower surface potentials 

observed in the upper left and right regions within the five-monolayer-thick film (Fig. 6.7d and 

e) suggest that in these areas the molecules may adopt an opposite net dipole moment, 

presumably with the phenyl group facing upwards in the topmost layer. Additionally, the six-

monolayer region delineated by the dashed square also features a lower SP compared to the 

bulk sample, which may indicate a head-to-head packing of bilayered molecules (Fig. 6.7d and 

f). 

 



126                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

 

Figure 6.7. Topography (a) and surface potential (d) mappings of a blade-coated polycrystalline Ph-BTBT-C10 

thin film under room temperature (27 ℃). Cross-sectional profile analysis along the dashed line, focusing on 

height (b) and surface potential (e). Histograms displaying the distribution of heights (c) and surface potentials (f) 

within the dashed square region (2.5 µm × 2.5 µm). Layer numbers identified from local film thickness are denoted 

on the relevant panels. 

 

By gradually increasing the sample temperature using a programmable stage equipped with an 

external thermocouple, we explored the thermal effects on thin-film morphology and molecular 

orientation. As illustrated in Fig. 6.8 (refer to Fig. A3.6 and A3.7 for a full catalogue of KPFM 

scans and analyses), no noticeable changes in topography were observed from RT to 

temperatures approaching 80℃ as shown in Fig. 6.8 a and d. While the global surface potential 

remained stable, an enhancement of SP in the 6-monolayer region, which was assumed to 

exhibit head-to-head bilayer packing at RT, is clearly resolved when comparing the SP 

mappings at 40℃ and 80℃. Further examination of the SP distribution within the nearby 

region, marked by the dashed squares in Fig. 6.8b and e, reveals that the peak corresponding 

to even-numbered layers merges with its odd-numbered counterpart as the temperature 

increases. This observation suggests an increase in molecular disorder within the originally 

ordered bilayer molecular stacks, echoing prior analyses of UV/Vis absorption spectra where 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   127 

 

  

a gradual decay in peak intensity ratio and the disappearance of sharp apex-like features 

indicate enhanced molecular disorder with rising temperature in drop-cast crystals. 

 

 

Figure 6.8. In-situ topography and surface potential mappings of a blade-coated polycrystalline Ph-BTBT-C10 

thin film at temperatures of 40℃ (first row) and 80℃ (second row). The histograms in panel c and f display the 

distribution of SP within the dashed square region (2.5 µm × 2.5 µm) which encompasses the 6-monolayer 

segment. 

 

However, as the temperature was further raised – corresponding roughly to the onset of regime 

Ⅱ in device measurements – an interesting elongation of thick molecular stacks towards a tilted 

in-plane direction started to emerge (as indicated by dashed circles in Fig. 6.9b). Given this 

small molecule is relatively lightweighted and film constituents are held together by weak 

interactions among alkyl chains and phenyl groups, molecules adjacent to the voids within the 

film or areas with mismatched layer thickness are probable to take advantage of thermal energy 

and diffuse along the topmost topography. This movement helps to release mechanical strain 

and achieve a more energetically favourable geometry. With a further elevation of temperature 



128                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

up to 100 ℃, we noticed that the dark regions within the film began to expand significantly, 

and even coalesced with nearby gaps and layer fringes (Fig. 6.9c). At room temperature, these 

dark regions are primarily composed of the exposed bottom substrate surface, characterized by 

its inherent roughness, and a partial coverage of a disordered monolayer of Ph-BTBT-C10, 

giving rise to an average thickness of less than 2 nm (Fig. A3.8a). Their expansion disrupts the 

connectivity of thin films and limits in-plane charge transport, resulting in a significant decline 

in the OFET drain current and charge carrier mobility. The coefficient of thermal expansion 

for organic semiconductors is typically much greater than that of oxide dielectrics, and the 

mismatch between consecutive layers has been reported by Mei et al. in an early study as a 

source of inhomogeneous strain and electronic trap density306. Furthermore, thermal expansion 

of molecular crystals is often highly anisotropic, and in some cases, negative uniaxial 

expansion of the crystal structure has been predicted307. Regarding Ph-BTBT-C10, earlier 

studies via temperature-dependent X-ray powder diffraction have shed light on an increase of 

the lattice constant b and a decrease in the monoclinic angle β with rising temperature towards 

the crystalline-SmE phase transition294. It is not entirely clear whether the preferred elongation 

direction observed in our microscopic characterizations follows the reported trend, since in 

blade-coated films, the shearing process induces extra contributions of lattice strain180 and thus 

complicates the analysis of thermal expansion in molecular layers.   

 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   129 

 

  

 

Figure 6.9. Temperature-dependent surface topography of a blade-coated polycrystalline Ph-BTBT-C10 thin film 

within Regime Ⅱ and Ⅲ. Each panel displays the height imaging at a specific temperature, indicated in the lower 

left corner. Dashed circles highlight emerging features with increasing temperature, as detailed in the main text. 

 

Assuming that the concentration of expanding voids in a thin film remains low at moderately 

high temperatures, it is plausible that, upon gradual cooling the deformation in the film 

microstructure could be at least partially reversible, potentially allowing for some recovery of 

electrical conductance. However, a substantial number of disconnected regions formed as the 

temperature rises to 110 ℃. And more intriguingly, the diffusion and reorganization of 

molecules led to creation of new aggregates, as highlighted in the lower right circle in Fig. 6.9d. 

From the topography mapping, the especially bright grains correspond to molecular stacks of 

nine monolayers (and above). The diffusion of molecules is further evidenced by an increased 

thickness in the dark “gap” regions, where the average height at 110℃ has risen to around 2.6 

nm, equivalent to the full length of an upright-standing Ph-BTBT-C10 monolayer (Fig. A3.8b). 

A complete and irreversible change in morphology occurred as expected when the temperature 

exceeded 120 ℃ (Fig. 6.9e). The discontinuous network of molecules failed to support the 

formation of an intact channel for field-induced charge carriers to transit through, ultimately 



130                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

leading to a complete breakdown of the electrical functionality. It is worthwhile noting that 

sublimation of these organic molecules is unlikely to take place within these temperature ranges. 

Admittedly, conducting a detailed thermogravimetric analysis would be beneficial to determine 

whether our blade-coated molecular layers exhibit the high thermal stability previously 

reported.  

 

Examination of the surface potential in Fig. 6.10 provide insights into the underlying evolution 

of molecular orientation as the temperature transitions through Regime Ⅱ to Regime Ⅲ. The 

correspondence of SP to layer numbers was well maintained even at very high temperatures, 

as shown in the histograms of SP distribution (Fig. 6.10e – h). The dominant peak with the 

highest SP is associated with the odd-numbered monolayers (denoted with the letter “O”), 

while their centre position shifted notably towards lower SP values as the temperature increases, 

likely due to a systematic drift generated by the equipment. The corresponding peak for even-

numbered monolayers, represented by the letter “E”, lies very close to and may be obscured by 

the prominent “O” peak. At temperatures reaching 110℃ when significant portions of “gap” 

regions appear, their low SPs (denoted by the letter “G”) contribute significantly to the overall 

distribution, as indicated in Fig. 6.10g and h. The consistency of SP among new aggregates of 

odd-numbered molecular stacks due to molecular diffusion suggests that the accretion of 

molecules at very high temperatures results in head-to-head packing between consecutive top 

bilayers.  

 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   131 

 

  

 

Figure 6.10. a-d, Surface potential mappings of a blade-coated polycrystalline thin film at various high 

temperatures. e-h, Distributions of surface potential within the square region (2.5 µm × 2.5 µm) at each 

temperature. The insets illustrate the corresponding height distribution with identified layer numbers marked 

among the peaks. “G” represents the SP peak associated with the dark “gap” regions, while “E” and “O” refer to 

the peaks for even- and odd-numbered monolayers, respectively. 

 

Another peculiar observation was revealed by investigating the evolution of the cross-sectional 

profile along the 5-monolayer regions with opposite net dipole moments, as indicated by the 

dashed lines in Fig. 6.7. The full temperature-dependent scans and analyses are summarised in 

Fig. A3.9 in the Appendix. From RT to 100℃, the left side of the 5-monolayer segment 

(denoted by “L” in Fig. 6.11) consistently exhibits a lower SP than the right side (denoted by 

“R”). When the temperature exceeded 110℃, the dark “gap” area adjacent to segment “L” 

expanded significantly, as seen in the upper left part of Fig. 6.9d and e, resulting in considerable 

shrinkage in the coverage of the “L” segment. Despite relatively flat heights being observed 

across this segment, it is puzzling to note that the surface potential profile exhibits a slope rising 

from the exposed bottom surface towards the high SP plateau, as indicated in Fig. 6.11g and h. 

We hypothesize that as the increasing temperature facilitates the dewetting of OSC films, 

regions close to film voids or with mismatch in molecular packing are more susceptible to 

enhanced molecular disorder. Consequently, the previously uniform alignment of upward-



132                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

facing phenyl groups at lower temperatures has been substantially perturbed, leading to a 

gradual transition from the low SP of the exposed bottom surface to the high SP among the 

right portions.  

 

 

Figure 6.11. Height (first row) and surface potential (second row) profiles along the cross-section over the 5-

monolayer regions, as marked by the dashed black line in Fig. 6.7, at various high temperatures. “L” and “R” 

correspond to the 5-monolayer segments that exhibit low and high SP at lower temperatures. 

 

6.4 Summary 

Combining field-effect transistor (FET) measurements with structural and morphological 

analyses using temperature-dependent UV-Vis absorption spectroscopy, thin-film X-ray 

diffraction, and in-situ Kelvin probe force microscopy, we investigated the charge transport 

properties within Ph-BTBT-C10 thin films as the temperature increased from room temperature 

(RT) and approached the threshold of the crystalline-to-smectic E (SmE) phase transition. From 

RT to moderate temperatures of below 80℃ (previously identified as Regime Ⅰ), the charge 

carrier mobility extracted from FET transconductance decays gradually as a result of enhanced 

scattering by lattice phonons and possibly impurities. The elevation of surface potential over 

the 6-monolayer region suggests that the exact cancellation of opposite molecular dipoles 

within a bilayer of head-to-head packing is weakened due to enhanced molecular disorder, 



Thermal Effects and Phase Transitions in Organic Thin-Film Transistors                                                                   133 

 

  

likely contributing to the degradation of carrier mobility. At temperatures exceeding ca. 80℃, 

thermal expansion and molecular diffusion noticeably set in, leading to morphological 

deformations primarily observed in the topmost molecular layers adjacent to gap areas and 

regions with mismatched layer thickness. With the continuous input of thermal energy, the gap 

areas –  indicative of substrate surfaces partially enclosed by disordered monolayers of 

molecules – expand dramatically and introduce a large number of disconnected grains within 

the bulk of the film. Hence, we observed highly unstable device performance and a drastic drop 

in mobility within this temperature regime Ⅱ. As long as the proportion of gaps is still limited 

and there are no prime thermal cracks or ruptures that span large areas over the 

(poly-)crystalline film, the original molecular orientation and charge transport capability can 

be at least partially recovered once the temperature is slowly reduced. The recovery is 

evidenced by device measurement conducted over extended periods and X-ray diffraction 

patterns obtained before and after subjecting the film to a thermal stress within the temperature 

range of regime Ⅱ. At sufficiently high temperatures (regime Ⅲ, although the phase transition 

temperature of ~143℃ has not yet been reached), molecular diffusion can result in dramatic 

transformations in surface topography, featuring bilayer head-to-head aggregations that 

resemble the Stranski-Krastanov (layer-plus-island) mode of crystalline thin film growth on 

lattice-mismatched substrates. Owing to a clear correlation between the oddness or evenness 

of layer numbers and the magnitude of surface potentials, we infer that the dewetted film at 

very high temperatures predominantly consists of stacks of odd-numbered monolayers 

(exhibiting higher SPs) alongside a large portion of exposed bottom surfaces (displaying lower 

SPs). This molecular reorganization fails to support a conducting channel, leading to 

irreversible transistor failure, accompanied by drastic morphological variations readily 

observable under an optical microscope. In this high-temperature regime, increasing disorder 

in the out-of-plane molecular orientation also manifests as a transition from a uniform SP 

distribution to a progressively ascending profile at locations adjacent to film voids, where the 

5-monolayer film was previously characterized by lower SPs compared to the bulk. Such 

deductions of enhanced molecular disorder are echoed in the absorption features of drop-cast 

thin crystals, characterized by a blue-shift in the (0-0) transition peak and a diminished intensity 

ratio of (0-0) to (0-1) bands as the temperature continuously rises. 



134                                                            Thermal Effects and Phase Transitions in Organic Thin-Film Transistors 

 

This study sheds light on a more comprehensive perspective on the impact of thermal treatment 

on the morphology and molecular disorder within crystalline thin films of OSCs, proposing 

effective methodologies for characterizing the thermal stability of thin-film transistors308–310. 

By incorporating an insertion layer at the semiconductor-dielectric interface or switching to 

another dielectric material with proper coefficients of thermal expansion, it is theoretically 

possible to mitigate the detrimental effects of thermal expansion and morphological reshaping. 

It would enable a more accurate examination of the intrinsic charge transport properties as the 

alkylated BTBT derivative approaches the phase transition. While device-scale measurements 

offer direct visualization, they can be influenced by a variety of external factors, making them 

less informative for studying subtle changes. Therefore, a holistic approach that integrates a 

variety of experimental tools—from optical and structural to microscopic perspectives—is 

essential for a thorough understanding of the dynamic processes in molecular solids.



 

Chapter 7 Conclusions and Outlook 

Over recent decades, significant strides have been made in identifying the crucial molecular 

structure requirements for achieving high carrier mobilities, and in developing a theoretical 

framework to rationalize the experimentally observed differences across various organic 

materials. Molecular semiconductors, characterized by their soft van-der-Waals bonds, exhibit 

fascinating charge transport physics in which static disorder, structural dynamics, and charge 

carrier motion are closely intertwined. This thesis presents a systematic exploration of the 

relationship between thin-film crystallinity and charge transport properties, maintaining a 

consistent chemical composition of the molecule throughout the study. In Chapter 4, we 

demonstrate that structural order profoundly influences the temperature dependence of carrier 

mobility, transitioning from typical band-like transport mechanisms to a more intricate scenario. 

Varying contributions from both delocalized and localized carriers occur simultaneously and 

result in temperature-induced shifts across different transport regimes. By analysing the 

electronic density of states near the band edge of the OSC active layer within a field-effect 

transistor, we gain essential insights into how charge transport phenomena are modified by the 

presence of traps, providing a deeper understanding of the transport physics in organic 

semiconductors. 

 

One of the paramount challenges discussed in this thesis for widespread adoption of OFETs is 

to enhance the stability and reliability over extended periods. In Chapter 5, we identify an 

intrinsic origin of charge carrier trapping, which is linked to uncancelled molecular dipoles 

oriented perpendicularly to the substrate. These thermodynamically metastable phases form 

during the meniscus-guided coating process and are particularly prevalent near the contact 

edges in a bottom-contact, bottom-gate configuration. This occurrence is likely due to large 

energy and height mismatches at the interface. We emphasize that precise device engineering 



136                                                                                                                               Conclusions and Outlook 

 

– including optimized deposition of OSC molecules, avoiding intrusive deposition of top 

contacts, and effective passivation of charge trapping at the dielectric interface – can 

substantially mitigate the stress instability of OFETs. Such improvements are instrumental in 

paving the way for the development of stable and high-performance FETs for the next-

generation of large-area, low-cost electronics. 

 

The advancements in space exploration, smart textiles, and innovative automobile designs have 

driven technological demand for high-temperature durable electronics. Moreover, the post-

processing thermal annealing treatment on OSC thin films is believed as a straightforward 

method to manipulate crystallinity, grain size, and electrical properties of organic electronic 

devices. In Chapter 6, we systematically examine the in-situ device performance variations, 

structural changes, and morphological transformations of Ph-BTBT-C10 thin film transistors, 

as the sample temperature approaches the phase transition of the OSC molecule. We provide a 

detailed analysis of the dual effects of thermal treatment on the vertical assembly and in-plane 

arrangement of molecules. These molecular configurations are decisive as they determine the 

charge transport pathways and the overall performance of transistors at elevated temperatures. 

Probing the emergence of molecular disorder through precise tuning of temperature, pressure 

or doping levels remains a crucial subject of study to elucidate the transport properties of 

organic semiconductors, and to tailor their performance for versatile applications across 

various operational scenarios. 

 

Having recognized the remarkable progress made by the academic community and the 

contributions of this thesis to the field of organic electronics, we must now turn our attention 

to the unresolved problems that continue to impede further advancements311,312. The 

widespread adoption and integration of organic electronics requires achieving minimal 

variations and good matching among circuit elements, optimizing complementary devices for 

circuit design, and ensuring sufficient environmental and operational stability. These 

requirements primarily pose challenges in terms of the overall cost and research and 

development (R&D) effort. Organic semiconductors should be compatible and reproducible 



Conclusions and Outlook                                                                                                        137 

 

  

across a broad range of device processing procedures; yet, developing materials that can 

withstand typical photolithographic patterning steps remains a formidable task. Although the 

low-temperature solution-processing of OSCs partially meets the 'low cost' promise of flexible 

electronics, the field must also focus on developing scalable material synthesis and high-

throughput printing methods with sufficient resolution11. Another challenging objective is the 

realization of dense arrays of micrometre-sized thin-film transistors (TFTs) on a single 

substrate313,314. It has been projected that the simplest circuits for sensing operations, which 

rely on addressing non-volatile memories, would require approximately 100 TFTs per square 

centimetre. Meanwhile, the basic displays would demand over 5000 TFTs per square 

centimetre 315. Achieving the deposition of hundreds of thousands of organic films with 

controlled crystallization over large areas and precise registration – as necessary for multilayer-

based devices – could revolutionize the opportunities for advanced displays and circuitries. 

 

The unique flexibility, processability, and tunable electronic characteristics of organic 

semiconductors catalyse exploration into novel functionalities that meet the evolving demands 

of technology and society. The ability of some OSCs to conduct both electronic and ionic 

charge carriers leads to the formation of a peculiar electric double layer (EDL) when in contact 

with an electrolyte316–318. This EDL generates a significant, local electric field that can be 

harnessed for energy storage, charge transport, or light emission. Additionally, organic mixed 

ionic–electronic conductors can transduce electrical signals into ionic signals, a critical 

capability for interfacing electronics with biological systems that operate with organic ion 

pumps319,320. The interaction between an OSC and a living organism opens new possibilities 

for organic electronics. For instance, it may become feasible to combine these advantageous 

attributes to realize stretchable optoelectronic systems interfaced directly with soft biological 

systems for personal health monitoring or drug delivery321–323. Furthermore, the development 

of organic electronics is branching into new areas, including organic thermoelectrics324,325, 

bioelectronics, neuromorphic computing326,327, and Internet-of-Things (IoT) systems328,329. 

Given their small carbon footprint, primarily due to low-temperature processability, OSCs are 

also at the forefront of the shift towards “green electronics”, which considers not only reducing 



138                                                                                                                               Conclusions and Outlook 

 

environmental impact but also emphasizes biocompatibility and biodegradability330,331. These 

attributes of OSCs are expected to attract significant and growing interest in the foreseeable 

future. 

 

At the time of writing, artificial intelligence (AI)-driven methodologies have profoundly 

influenced various aspects of daily life and scientific research, extending into the field of 

organic electronics332–334. Large language models significantly expedite literature reviews and 

data analysis, enabling rapid and informed decision-making while focusing research efforts on 

innovation. Machine learning algorithms, trained on extensive databases, are adept at 

predicting the properties of organic semiconductor materials, thereby streamlining material 

screening and minimizing the need for trial-and-error approaches. Additionally, deep learning 

networks are essential for simulating and predicting material behaviour under diverse 

conditions, which is critical for device modelling and production line adjustments. These AI 

tools not only facilitate the design of new materials but also optimize manufacturing processes, 

significantly enhancing accuracy and efficiency. It is optimistic to anticipate that the integration 

of AI into organic electronics research and industry will continue to transform both scientific 

discovery and production processes. 

 

In conclusion, this thesis has explored critical aspects of charge transport mechanisms, 

structural order, and device stability in organic semiconductors, contributing valuable insights 

to their underlying physics. By examining thin-film crystallinity, metastable molecular phases, 

and the effects of thermal treatment, this work has uncovered new pathways for optimizing the 

performance of organic field-effect transistors. While significant strides have been made, 

challenges such as scalability, environmental stability, and high-resolution fabrication remain 

barriers to the widespread adoption of organic electronics. Looking ahead, the unique 

properties of organic semiconductors—such as their flexibility, biocompatibility, and low-

temperature processing—position them as key players in the development of next-generation 

technologies, including smart flexible electronics, bio-integrated systems, and the Internet of 

Things (IoT). The integration of artificial intelligence into material discovery and device 



Conclusions and Outlook                                                                                                        139 

 

  

engineering further opens new horizons for the field, enabling more efficient material screening, 

predictive modelling, and process optimization. This interdisciplinary fusion promises to 

revolutionize the landscape of organic electronics, propelling the field toward broader and more 

impactful applications. As organic semiconductors continue to evolve, their role in driving 

sustainable, high-performance electronic systems will undoubtedly become a defining factor 

in the future of technology. 



 

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Appendix A Supplementary Information for 

Experimental Chapters 

This appendix offers supplementary information for Experimental Chapters 4, 5, and 6. 

Detailed discussions of these results are elaborated upon in the main text. 

A.1 Characterizing Charge Transport and Trap Dynamics in 

OFETs across Temperature Variations 

 

Figure A1.1. Characterization of bottom-gate, bottom-contact FETs with spin-coated Ph-BTBT-C10 thin films. 

The channel width is of 1200 µm. Transfer characteristics in the linear (a) and saturation (b) regimes. c, Output 

characteristics at various fixed Vg. d, Optical micrograph of a representative device. e, Summary of device figures 

of merit. 

 



A2                                                                                              Supplementary Information 

 

Figure A1.2. Variable temperature measurements of a drop-cast thin-film transistor with contact modification. 

The source-drain voltage is set at -5 V. These results complement the findings discussed in the main text, 

demonstrating that a reduced contact resistance below 1 kΩ·cm can be achieved by inserting a molybdenum oxide 

layer beneath gold contacts. The mobility-temperature relationship is shown to be unaffected by contact effects.  

 

 

Figure A1.3. Gate voltage-dependent two-probe (a) and four-probe (b) mobility as a function of temperature, 

derived from the slope of curves shown in Fig. 4.8a and b. c, Two successive gate sweeps of the device shown in 

Fig. 4.7c from Vg = + 10 V to -100 V, conducted at 300 K. The slight shift between the two transfer curves resulted 

in a minor change in the slope of the linear fitting (a 6% increase in calculated mobility). This observation suggests 

that the dramatic increase in mobility at 300 K, which rises by around 1 cm2 V-1 s-1 compared to slightly lower 

temperatures, is unlikely to be an artefact caused by bias-stress degradation.  

 



Supplementary Information                                                                                              A3 

 

  

Figure A1.4. a, Identification of the turn-on voltage and the associated flat-band current from the linear-regime 

transfer curve. b, Extraction of the gate voltage at which the mobility saturates, with the corresponding interface 

potential assigned as the energy difference between the Fermi level and the valence band edge (panel c). 

 

 

Figure A1.5. Fitting parameters related to Eq. 4.8 for the Gaussian peaks in Fig. 4.10 and Fig. 4.11, depicting the 

trap DOS relative to the energy from the valence band edge. Panel a and b correspond to drop-cast and blade-

coated thin-film transistors, respectively. 



A4                                                                                              Supplementary Information 

 

A.2 Charge trapping and bias stress degradation in Ph-BTBT-

C10 thin-film transistors 

 

Figure A2.1. Decrease of the source-drain current at Vg = -30 V and Vd = -1V upon sweep-stress cycles. For the 

stress step, the device was exposed to either a gate voltage of -30 V while the source-drain contacts were grounded 

(black squares), or a source-drain voltage of -1 V while the gate was grounded (red squares). The latter condition 

gave rise to a negligible change in electrical characteristics, implying that the observed degradation is caused by 

the gate bias. 

 



Supplementary Information                                                                                              A5 

 

  

 

Figure A2.2. Decay of the source-drain current over 300 seconds under gate stress at -30, -40, and -50 V with Vd 

=-5 V. The black dashed curves correspond to fits using a stretched exponential (a-c) and a stretched hyperbola 

(d-e) function. The fitting parameters, the characteristic time constant τ and the stretching parameter β, are 

indicated in respective panels. At first glance the current ratio when the device was stressed at -50 V versus -40 

V appears to contradict with the intuition that a stronger gate field should result in more severe degradation. 

However, the observed trend in transfer characteristics indicates that the normalized current ratio after stress is 

lower when evaluated at a low gate voltage (less negative Vg) compared to a higher |Vg|. Hence, directly comparing 

the current ratios under varying stress and measurement conditions may not yield correct assessments. Notably, a 

shorter time constant τ indeed tells us that the current decay is faster in panel c/f than in panel b/e. 

 



A6                                                                                              Supplementary Information 

 

 

Figure A2.3. Bias stress characterization of the same top-contact, polycrystalline FET with a stress voltage of -

40 V between consecutive gate sweeps. Akin to earlier experiments conducted with a stress voltage of -30 V, the 

threshold voltage shift and current decay is more drastic during the initial two cycles.  

 

 

Figure A2.4. Bias stress characterization of an unstable bottom-contact, polycrystalline FET with electrodes 

prepared via shadow-mask evaporation. Compared to ideal devices, we noted a significant change in electrical 

parameters under bias stress and a pronounced downward trend in transfer curves at elevated gate voltages, 

indicative of charge trapping phenomena148. 

 



Supplementary Information                                                                                              A7 

 

  

 

Figure A2.5. Surface morphology of thermally deposited molybdenum oxide (a) and F4-TCNQ (b) on SiO2. 

Panel c shows the MoOx layer with a cross-sectional thickness of around 64 nm, exhibiting a uniform top surface. 

On the other hand, thermally deposited F4-TCNQ aggregates into variously sized islands and features a very rough 

top surface (d), despite having a similar nominal thickness as indicated by the evaporation process.   

 

 

Figure A2.6. Successive gated four-point-probe measurements of a top-contact polycrystalline FET. a, 

Extrapolated electrical potentials at the source and drain terminals, with a source-drain voltage of -1 V applied 

across the channel. b, Gate voltage dependence of channel and contact resistance. c, Changes in the proportion of 

contact and channel resistance relative to total resistance upon successive gate sweeps. These ratios were extracted 

at various levels of effective gate voltage to accommodate shifts in the transfer curves. 

 



A8                                                                                              Supplementary Information 

 

Figure A2.7. Temperature-dependent bias stress degradation concerning the threshold voltage shift from 100 K 

to 300 K, as determined through cyclic sweep-stress-regeneration measurements. Hollow circles correspond to 

the threshold voltages extracted from the initial gate sweep at each temperature. Solid circles represent the 

threshold voltages after nine repeated stress cycles. Hollow squares denote the threshold voltages after applying 

a final positive gate bias of 60 V for 5 min, before the temperature was raised by 25 K for subsequent 

measurements. Panel a shows the results from a top-contact polycrystalline device, while panel b illustrates data 

from a similar device but with contact doping using F4-TCNQ.  

 

 

Figure A2.8. Characterization of the Young’s moduli in polycrystalline Ph-BTBT-C10 thin films by AFM. a, 

Height (top panel) and Young’s modulus (bottom panel) measurements of a bottom-contact device. Despite 

variations in thickness and molecular disorder, 4 and 5 monolayers of Ph-BTBT-C10 exhibit similar elasticity. b, 

Height (top panel) and Young’s modulus (bottom panel) measurements of a top-contact device. The Au 

nanoparticles possessed a lower Young’s modulus than the Au electrode and diffused into the OSC film. 



Supplementary Information                                                                                              A9 

 

  

A.3 Thermal Effects and Phase Transitions in Organic Thin-

Film Transistors: Exploring Transport Properties and 

Structural Dynamics 

 

Figure A3.1. a – c, Optical micrographs of the blade-coated polycrystalline thin film under the increasing 

temperature ramp: at 26 ℃ (Regime I, a), 100 ℃ (Regime II, b), and 135℃ (Regime III, c). In Regime III, 

extensive linear-shaped cracks and point-like defects appear randomly across the film, signifying irreversible 

morphological destruction. d – e, Corresponding saturation-regime transfer characteristics illustrating the 

extracted mobility-temperature relationship in Fig. 6.3a (d) and Fig. 6.4a (e). 

 

 



A10                                                                                              Supplementary Information 

 

Figure A3.2. Evolution of linear-regime transfer characteristics of a blade-coated polycrystalline thin film 

transistor during storage. The source-drain voltage is set to -1 V. Day 0 denotes the date of device fabrication 

completion. a, Sample stored in air throughout the test duration. b, Sample subjected to extensive hotplate 

annealing at 80 ℃ and overnight vacuum annealing, ensuring that the enhancement in FET conductance is not 

related to the gradual withdrawal of residual solvents. c, Sample stored in a nitrogen-filled glovebox with minimal 

traces of oxygen and moisture (< 10 ppm).  

 

Figure A3.3. Example of Gaussian peak fitting applied to the UV-Vis absorption spectra, with the associated 

fitting parameters summarised in panel b. 

 



Supplementary Information                                                                                              A11 

 

  

Figure A3.4. UV-Vis absorption spectra of the thin film following rapid cooling from the smectic E phase to 

40 ℃. 

 

 

Figure A3.5. Example of Pseudo-Voigt fitting applied to the (001) peak in X-ray diffraction patterns. Associated 

fitting parameters and metrics for evaluating the goodness of fit are summarised in the inset. The mathematical 

expression for a pseudo-Voigt function is displayed on the right. Here, mu is a mixing parameter that accounts for 

the linear combination of a Lorentzian and a Gaussian profile, xc is the centre of the peak, and w is the FWHM. 

 



A12                                                                                              Supplementary Information 

 

 

Figure A3.6. In-situ topography (top row), surface potential (middle row), and surface potential distribution of 

the selected region as indicated in the main text (bottom row) within temperature Regime Ⅰ. No change in 

topography is observed, whereas the elevation of SP in the 6-monolayer segment suggests increased molecular 

disorder as the temperature rises. 

 



Supplementary Information                                                                                              A13 

 

  

 

Figure A3.7. In-situ topography (top row), surface potential (middle row), and surface potential distribution of 

the selected region, captured from 85℃ to 125℃. Colour scales are normalized across the same ranges for heights 

and voltages, while a drift in the SP to lower values at high temperatures results in mappings with dimmer features 

and reduced contrasts. 

 



A14                                                                                              Supplementary Information 

 

 

Figure A3.8. Histograms of the thin-film height distribution at 27 ℃ (a) and 110 ℃ (b). The inset of panel a 

shows the region of interest (3 µm × 3 µm) used for histogram plotting under room temperature, while the full 

height image is analysed for generating the histogram at 110℃. Interpretations of peaks are specified accordingly. 

 



Supplementary Information                                                                                              A15 

 

  

 

Figure A3.9. Cross-sectional height (upper row) and surface potential (lower row) profiles along the 5-monolayer 

region with opposite molecular dipoles, as indicated by the dashed line in Fig. 3.7, across various temperatures. 

 

 

 

 

 

 

 

 

 



A16                                                                                              Supplementary Information 

 

 

 



 

 

Appendix B Further Experimental Investigations 

This appendix details two separate experimental endeavours with promising potential for future 

research projects: (i) developing innovative techniques for OFET fabrication, and (ii) exploring 

charge transport physics at high carrier density in organic semiconductors. 

B.1 Transfer of Ph-BTBT-C10 thin films via a wet-etching 

method 

Solution-processable organic small molecules are often lauded for their versatility across 

various substrates and form factors ideal for flexible electronics, thanks to the low-temperature 

processability and inherent mechanical flexibility. Yet, nucleation and crystal growth are 

typically affected by factors such as surface energy, roughness, and resistance to organic 

solvents, among others, of the substrate or underlayer. For example, achieving spontaneous 

assembly of Ph-BTBT-C10 on hydrophobic surfaces like Cytop or ODTS-treated SiO2 is not 

straightforward with a conventional spin-coating or blade-coating method. Moreover, the top 

surface of an organic thin film tends to be more irregular and less controllable than the bottom 

interface, as the topmost morphology is shaped by solvent evaporation dynamics and shear 

forces imparted by the coating blade, compromising charge transport efficiency in a top-gated 

FET architecture. In this sense, transferring pre-deposited organic thin films emerges as a 

favourable approach, inspiring novel studies which include the epitaxy growth of molecular 

crystals on liquid surfaces335,336, peeling off thin films with PDMS stamps or thermal release 

tape337,338, and water exfoliation of OSCs with lyophobic side chains from superhydrophilic 

substrates339,340.  



B2                                                                               Further Experimental Investigations 

 

Conversely, valuable insights can be gleaned from the research of two-dimensional materials, 

in which transferring chemical vapour deposition (CVD)-grown graphene can involve applying 

a PMMA support layer atop, followed by wet etching of the underlying copper foil to free the 

PMMA/graphene composite. Here, we adopt a similar strategy to transfer blade-coated Ph-

BTBT-C10 films from their original deposition substrate to a new target surface. The detailed 

methodology is illustrated in Fig. A1a. Firstly, a copper layer of ~40 nm is thermally evaporated 

onto either glass or SiO2/Si substrates and exhibits sub-nanometer roughness (see Fig. A2d). 

Polycrystalline Ph-BTBT-C10 thin films are deposited by blade coating atop the copper layer. 

In constructing top-contact devices in a simple manner, gold electrodes were fabricated 

similarly via thermal evaporation, followed by encapsulation of the substrate with Cytop. This 

Cytop layer acts as a rigid support, ensuring the structural integrity of the composite during the 

subsequent copper etching. The copper is then dissolved using a ferric chloride-based etchant 

(Copper etchant, Sigma Aldrich), leaving the Cytop/OSC composite floating on the etchant 

solution surface, from where it can be readily collected by the destination substrate. Fig. A1b-

d illustrate the typical electrical characteristics of a bottom-gate, top-contact device employing 

a transferred film on a fresh SiO2/Si substrate. The linear-regime transfer curve shows notable 

linearity at a source-drain voltage of -1 V, along with a reasonably good mobility; whereas, an 

increased gate leakage current is observed in the subthreshold region. The bump in |Ig| is 

presumably due to the lacking of fine patterning on the transferred Cytop/OSC composite film, 

leading to a rise in the displacement current during the transient process of conducting channel 

formation.  

 



Further Experimental Investigations                                                                               B3 

 

  

 

Figure A.1. a, Wet transfer process of polycrystalline Ph-BTBT-C10 thin film via etching of the underlying copper 

layer. b, Linear-regime transfer characteristics of a bottom-gate, top contact FET on a new SiO2/Si substrate, 

featuring a transferred OSC film. c, Gate voltage dependence of mobility, as extracted from the transfer curve in 

b. d, Evolution of threshold voltage and peak source-drain current at Vg = -30 V, where the device undergoes 

biasing for 20 seconds with Vg = -20 V between successive gate sweeps. 

 

It is noteworthy to comment that the stress stability of transferred film-based OFETs appear to 

be inferior to those reported in the main chapters. As indicated in Fig. A.1d, the device 

experiences a shift of the threshold voltage by almost -4V after undergoing nine cycles of gate 

biasing at -20V for 20 seconds each, alongside a nearly 10% decay in the source-drain current 

at a gate voltage of -30V. Several factors could contribute to this result.  First, despite thorough 

rinsing in DI water and hours of annealing on a hotplate post-wet transfer, the potential for 

residual water molecules or mobile ions to remain under the composite film cannot be 

discounted, especially considering the hydrophobic and moisture-resistant qualities of Cytop. 

Given that the initial threshold voltage and off-current level align with those of devices 

comprising directly coated polycrystalline films, the presence of impurities is presumed 

minimal. Nevertheless, X-ray Photoelectron Spectroscopy (XPS) analysis of elemental 

composition would be beneficial to verify any remnants following the etching and rinsing 

procedure. The morphology of blade-coated Ph-BTBT-C10 on copper was examined by AFM, 



B4                                                                               Further Experimental Investigations 

 

as shown in Fig. A2. In some regions, the topmost layer forms sporadic islands, suggesting a 

thin-film growth pattern similar to that on silicon dioxide surfaces. These islands typically 

exhibit a step height of approximately 2.6 nm or 5.2 nm, correlating to the longitudinal length 

of a Ph-BTBT-C10 molecule or the height of a bilayer, respectively. Pin holes or cavities are 

present in both the topmost islands and the more densely packed bottom layer, where exposed 

copper surfaces distinguish from the bulk in texture and phase. The overall thickness of the 

bulk film measured against the exposed substrate is around 10 nm, equating to four monolayers 

frequently observed in films prepared using the specific blade coating recipe. One might 

question the homogeneity of the bottom interface post-etching, yet uncovering the OSC side 

of the floating film poses its own set of challenges. Directly flipping and retrieving the film 

from the etchant proves to be impractical. An alternative approach involves attaching the Cytop 

side to a solid substrate before immersion, then flipping the sample after the copper underlayer 

has been etched away. Our attempts using polydimethylsiloxane (PDMS) or cyanoacrylate 

superglue as both adhesive and holder for the composite film, however, led to significant 

surface distortions on the exposed OSC interface. These distortions, characterized by wrinkles, 

crumples, and humps, were unlikely a result of the copper etching process but rather due to 

strain-induced interplay at the adhesive/Cytop interface. 

 



Further Experimental Investigations                                                                               B5 

 

  

Figure A.2. a, AFM height and phase images of a polycrystalline Ph-BTBT-C10 thin film blade-coated on an 

evaporated copper surface. b, Cross-sectional profile along the indicated white line reveals terraced structures, 

with step sizes corresponding to multiples of the long-axis molecular length of Ph-BTBT-C10. c, AFM height and 

phase scan of the bottom OSC interface after Cu etching, supported by a PDMS layer on glass. d, Surface 

morphology of the evaporated copper layer illustrates a root-mean-square roughness below 200 pm. 

 

In summary, our mini-study explored the adaptation of a copper etching technique, traditionally 

used in graphene sample preparation, for the wet transfer of blade-coated Ph-BTBT-C10. The 

resulting bottom-gate, top-contact OFETs, featuring transferred films on new substrates, 

exhibited commendable electrical characteristics, despite some compromises in stress stability. 

Efforts were made to assess the morphology of the small molecule on the copper surface and 

to evaluate the structural uniformity of the OSC bottom interface. However, additional practice 

focused on contaminant identification, electrochemical analysis (e.g. examining whether the 

acidity of the etchant solution would affect electronic properties of the small molecule), and 

the attainment of a defect-free bottom interface post-etching is necessary. Such studies are 

crucial for further validating the efficacy of this transfer technique and refining the procedure 

for more consistent device manufacturing. 



B6                                                                               Further Experimental Investigations 

 

B.2 Thermoelectric voltage characterization of ion-gel gated Ph-

BTBT-C10 

Beyond assessing the temperature and gate voltage dependence of field-effect mobility in 

OFETs, the Seebeck coefficient represents another important yet less focused transport 

coefficient for probing charge transport in organic semiconductors. When a temperature 

gradient ΔT is applied across a conducting solid, charge carriers migrate from the warmer to 

the cooler end, generating an internal electric field to counterbalance the charge diffusion. This 

built-in electromotive force Vtherm, known as the thermal or thermoelectric voltage, is first-order 

related to the Seebeck coefficient S as S = Vtherm/ΔT. From a thermodynamic perspective, the 

Seebeck coefficient quantifies the entropy transported by each thermally excited charge carrier 

divided by its charge341. A general expression for the electronic contribution to S is given by 

 B F

B

Ek E E
S dE

e k T




 
  

 
 ,                                           (A. 1) 

where kB is the Boltzmann constant, σ(E) denotes the electrical conductivity that reflects the 

shape of the density of states (DOS) function and energy-dependent scattering or trapping 

mechanisms,  E dE    represents the total conductivity, and T is the temperature342. It is 

self-evident that the Seebeck coefficient would vary with the gate voltage in a conventional 

FET geometry due to a controlled modulation of the Fermi level. Utilizing ion-gel gating, a 

technique allows for electrostatic doping of alkylated molecular semiconductors without 

triggering undesired chemical reactions, one may achieve an exceptionally high charge carrier 

concentration at the semiconductor/electric double-layer interface343,344. This approach enables 

us to surpass the limitations associated with measuring thermopower as a function of gate 

voltage using standard solid-state dielectrics345–349. By simply adjusting the gate voltage, it 

becomes feasible to separate the temperature dependence of the Seebeck coefficient, thereby 

illuminating aspects of the charge transport mechanism. For instance, in scenarios where 

hopping carriers significantly interact with the molecular lattice, leading to phonon mode 

softening or hardening, this carrier-induced lattice vibrational entropy can substantially 

increase the Seebeck coefficient—a phenomenon that is independent of charge concentration350. 



Further Experimental Investigations                                                                               B7 

 

  

Such insights are invaluable for understanding the charge transport dynamics and the nature of 

electronic states in high-mobility organic semiconductors351,352. 

 

 

Figure A.3. a, Schematic of the integrated chip and device architecture used to perform ion-gel gated 

measurements of the Seebeck coefficient in single-crystalline Ph-BTBT-C10 thin films. b, Transfer characteristics 

and extracted channel sheet conductivity of the test sample at room temperature, with a source-drain voltage set 

at -0.1 V.  

 

We employed the microchip architecture and measurement sequence developed by our group 

to probe the thermal voltage of single-crystalline Ph-BTBT-C10 in response to ion-gel gating. 

The approach aims to reduce errors or inconsistencies that arise from voltage or temperature 

difference extrapolation when using external heaters or Peltier elements. Figure A.3a illustrates 

the schematic design of the device, which integrates thermally evaporated MoOx/Au FET 

source and drain electrodes as two resistance temperature sensors, and a stripe heater isolated 

from the patterned OSC crystal to establish a controllable transverse temperature differential. 

An ion gel film was spin-cast from an acetone solution in advance in which the cations and 

anions of an ionic liquid 1-Butyl-1-methylpyrrolidinium [BMP] and 

bis(trifluoromethylsulfonyl)imide [TFSI] are enclosed by poly(vinylidene fluoride-co-

hexafluoropropylene) (P(VDF-HFP)) networks. The film was placed on top of the device 

channel followed by lamination of a gold foil which serves as the top gate electrode. To 

mitigate gate leakage and perturbation from gate potential, we attempted to measure the built-



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in thermal voltage as a function of heater power (temperature differential) under high vacuum 

at a low temperature of ~220 K. At such low temperatures, transverse ion migration within the 

electrolyte is restricted, making it an optimal condition for accurate measurements. Hence, a 

prerequisite involves gently stressing the device with a set gate voltage while cooling it down 

from a moderate temperature of around 260 K to the target low temperature. The temperature 

difference across the organic semiconductor is determined by measuring the respective 

resistance of two temperature sensors relative to the heater power. And the temperature 

coefficient of resistance (TCR) of these on-chip thermometers should be pre-calibrated by 

scanning their resistance at various cryostat temperatures. With the TCR established, it is 

possible to calculate the temperature difference corresponding to each level of heater power. 

Finally, the Seebeck coefficient is derived from fitting the thermal voltages across multiple 

temperature differentials. 

Figure A.4. a,c Thermal voltage as a function of a parabolic sweep in heater power at 220 K, following gate-

stress at -2.5 V during cooling from 260 K. The hot-end (cold-end) thermometer is grounded. Heater and gate 

biases were held for 30 seconds each. b,d, Thermal voltage as a function of calculated heater power, with the hot-

end (cold-end) thermometer grounded and the other left floating. Thermal voltage values were determined by 

averaging 20 sampling points, and the standard error is depicted as the error bar. 

 



Further Experimental Investigations                                                                               B9 

 

  

Due to time constraints, we only managed to measure the thermal voltage as a function of 

applied heater power with a specific gate voltage of -2.5 V, which subjected the ion gel to a 

substantial electric bias. Unfortunately, the test device broke down during a second cool-down 

under a different gate voltage stress, exhibiting minor fractures in the gold strips across the 

channel region. We suspect that these damages stemmed from mechanical stress during rapid 

temperature changes under bias, particularly as a probe was pressed against the gold foil 

(attached to the ion gel and device channel) for continuous gate voltage application. This 

incident hindered our ability to calibrate the TCR of temperature sensors and accurately 

determine the Seebeck coefficient from the test device. However, the preliminary results 

underscore the viability of ion-gel gated Seebeck measurements, contingent on meticulous 

device handling and measurement protocol. The channel sheet conductivity, as shown in Fig. 

A3b, can reach a few microsiemens at a gate voltage of around -2 V, which, while promising, 

remains an order of magnitude lower than the state-of-the-art values from molecular 

semiconductors reported in the literature351. This deficit is likely due to imperfect crystallinity 

of the OSC top surface, resulting in suppressed mobility. Additionally, it is presumed that  the 

insulating alkyl side chains can separate the ionic liquid from the pi-conjugated core, thereby 

minimizing the risk of unwanted electrochemical reactions at the OSC/EDL interface353,354; 

this premise should be re-examined for molecular semiconductors that are asymmetrically 

alkylated. As displayed in Fig. A4b, the obtained thermal voltage data points closely aligned 

with the linear trend within the error margin, suggesting that higher heater power inputs could 

yield thermal voltages in the order of several hundred microvolts. The reliability of the thermal 

voltage measurements was verified by reversing the grounding from the hot-end to the cold-

end thermometer, giving rise to a similar linear relationship between thermal voltage and heater 

power (Fig. A4d), albeit with an inverse gradient sign (8.436 ± 0.258 vs -8.246 ± 0.111 

µV/mW), reinforcing the credibility of this methodology. 

 



B10                                                                               Further Experimental Investigations 

 

 

Figure A.5. Thermal voltage calibration measurement. a, Variation of the resistance of two temperature sensors 

as a function of heat power at 220 K. The heater bias was maintained for 1 minute and each obtained resistance 

value was averaged over 20 samples. The sweep of heater power and stripe resistance of the hot-end and cold-end 

thermometers were displayed in b and c, respectively. 

 

In summary, our study sought to probe the thermal voltage of single-crystalline Ph-BTBT-C10 

thin films using an integrated on-chip heater and ion gel gating. A perfect fit between thermal 

voltage and heater power, or equivalently the temperature differential across the organic 

semiconductor, was observed at 220 K, when ion immobilization in the ionic liquid ensures a 

mitigated gate leakage and an improved signal-to-noise ratio. We anticipate obtaining thermal 

voltages exceeding 100 µV with increased heater power. As shown in Fig. A5, resistance 

measurement of temperature sensors against heater power proves the effectiveness of these 

MoOx/Au stripe thermometers, each exhibiting resistance below a kilo-ohm. Time constraints 

and device failure during a secondary cooling prevented us from characterizing the TCR and 

determining the actual temperature differential and, by extension, the Seebeck coefficient of 

the test device. This practice suggests that extra precautions might be taken to alleviate thermal 

or mechanical stress on the sample. An additional concern pertains to the bias stability of the 

device, given that the ion gel and OSC films are likely to retain some moisture during device 



Further Experimental Investigations                                                                               B11 

 

  

preparation in ambient conditions. However, we expect that under high vacuum and low 

temperature, the shift in device onset could be minimised by meticulously managing the biasing 

conditions. By measuring the Seebeck coefficient as a function of gate bias applied through ion 

gel, it is promising to explore charge scattering mechanisms and polaronic effects in molecular 

semiconductors under surface charge densities unachievable with traditional solid-state 

dielectrics. This approach may also illuminate charge carrier correlations at low temperatures, 

offering deeper insights into the charge transport physics governing high-performance organic 

semiconductors. 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



B12                                                                               Further Experimental Investigations